Renesas M16C/62P Series Hardware Manual page 85

M16C/62P Group (M16C/62P, M16C/62PT)
(1) Separate Bus, No Wait Setting
(2) Separate Bus, 1-Wait Setting
(3) Separate Bus, 2-Wait Setting
NOTES :
1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.
Figure 8.7 Typical Bus Timings Using Software Wait (1)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Bus cycle
BCLK
Write signal
Read signal
Data bus
Address bus
CS
Bus cycle
BCLK
Write signal
Read signal
Data bus
Address bus
CS
Bus cycle
BCLK
Write signal
Read signal
Data bus
Address bus
CS
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(1)
Bus cycle
Output
Address Address
(1)
Bus cycle
Output
Address
(1)
Output
Address
(1)
Input
(1)
Input
Address
(1)
Bus cycle
Address
010-62245566 13810019655
8. Bus
Input