Renesas M16C/62P Series Hardware Manual page 225

M16C/62P Group (M16C/62P, M16C/62PT)
(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
SCLi
SDAi
(2) IICM2= 0, CKPH= 1 (clock delay)
SCLi
SDAi
(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0
SCLi
SDAi
(4) IICM2= 1, CKPH= 1
SCLi
SDAi
i=0 to 2
This diagram applies to the case where the following condition is met.
· UiMR register CKDIR bit = 0 (Slave selected)
Figure 17.26 Transfer to UiRB Register and Interrupt Timing
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
1st bit 2nd bit 3rd bit 4th bit 5th bit
D7 D6 D5 D4
1st bit 2nd bit 3rd bit 4th bit 5th bit
D7 D6 D5 D4
1st bit 2nd bit 3rd bit 4th bit 5th bit
D7 D6 D5 D4
1st bit 2nd bit 3rd bit 4th bit 5th bit
D7 D6 D5 D4
b15
•••
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提供单片机解密、IC解密、芯片解密业务
6th bit 7th bit 8th bit 9th bit
D3 D2 D1 D0 D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
6th bit 7th bit 8th bit 9th bit
D3 D2 D1 D0
D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
6th bit 7th bit 8th bit 9th bit
D3 D2 D1 D0 D8 (ACK, NACK)
Receive interrupt
Transmit interrupt
(DMA1 request)
Transfer to UiRB register
b15
6th bit 7th bit 8th bit 9th bit
D3 D2 D1 D0 D8 (ACK, NACK)
Receive interrupt
(DMA1 request)
Transfer to UiRB register
b9 b8 b7 b0 b15
D0 D7 D6 D5 D4 D3 D2 D1
UiRB register
17. Serial Interface
b9 b8 b7 b0
••• D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
b9 b8 b7 b0
••• D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
b9 b8 b7 b0
••• D0 D7 D6 D5 D4 D3 D2 D1
UiRB register
Transmit interrupt
Transfer to UiRB register
b9 b8 b7
••• D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
010-62245566 13810019655
b0