Renesas M16C/62P Series Hardware Manual page 277

M16C/62P Group (M16C/62P, M16C/62PT)
Port Pi Direction Register (i=0 to 7 and 9 to 13)
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. Make sure the PD9 register is w ritten to by the next instruction after setting the PRC2 bit in the PRCR register to "1"
(w rite enabled).
2. During memory extension and microprocessor modes, the PDi register for the pins functioning as bus control pins (A0
to A19, D0 to D15, CS0
3. To use ports P11 to P14, set the PU37 bit in the PUR3 register to "1" (enable).
Port P8 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
Figure 21.7 PDi Registers
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Symbol
PD0 to PD3 03E2h, 03E3h, 03E6h, 03E7h
PD4 to PD7 03EAh, 03EBh, 03EEh, 03EFh
PD9 to PD12 03F3h, 03F6h, 03F73h, 03FAh
PD13 03FBh
Bit Name
Bit Symbol
PDi_0 Port Pi_0 Direction Bit
PDi_1 Port Pi_1 Direction Bit
PDi_2 Port Pi_2 Direction Bit
PDi_3 Port Pi_3 Direction Bit
PDi_4 Port Pi_4 Direction Bit
PDi_5 Port Pi_5 Direction Bit
PDi_6 Port Pi_6 Direction Bit
PDi_7 Port Pi_7 Direction Bit
_____ _____ ___ ______ ___
to CS3 , RD , WRL /WR , WRH
Symbol
PD8
Bit Symbol
PD8_0 Port P8_0 Direction Bit
PD8_1 Port P8_1 Direction Bit
PD8_2 Port P8_2 Direction Bit
PD8_3 Port P8_3 Direction Bit
PD8_4 Port P8_4 Direction Bit
— Nothing is assigned. When w rite, set to "0".
(b5) When read, its content is indeterminate.
Port P8_6 Direction Bit
PD8_6
Port P8_7 Direction Bit
PD8_7
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提供单片机解密、IC解密、芯片解密业务
(1, 2, 3)
Address
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 7 and 9 to 13)
______ _____ _____ _______
/BHE , ALE, RDY , HOLD
Address
03F2h
Bit Name
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
21. Programmable I/O Ports
After Reset
00h
00h
00h
00h
Function
_______
, HLDA and BCLK) cannot be modified.
After Reset
00X00000b
Function
010-62245566 13810019655
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
RW
RW