Renesas M16C/62P Series Hardware Manual page 233

M16C/62P Group (M16C/62P, M16C/62PT)
17.1.4.1 Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the
UiSMR3 register and the CKPOL bit in the UiC0 register.
Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.
Figure 17.30 shows the Transmission and Reception Timing in Master Mode (Internal Clock).
Figure 17.31 shows the Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock) while
Figure 17.32 shows the Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock).
Clock output
(CKPOL=0, CKPH=0)
Clock output
(CKPOL=1, CKPH=0)
Clock output
(CKPOL=0, CKPH=1)
Clock output
(CKPOL=1, CKPH=1)
Data output timing
Data input timing
Figure 17.30 Transmission and Reception Timing in Master Mode (Internal Clock)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
D0 D1
"L"
Page 218 of 390
提供单片机解密、IC解密、芯片解密业务
D2 D3 D4
17. Serial Interface
D5 D6 D7
010-62245566 13810019655