Renesas M16C/62P Series Hardware Manual page 193

M16C/62P Group (M16C/62P, M16C/62PT)
Main clock, PLL clock, or on-chip oscillator clock
(UART1)
RXD1
Clock source selection
CLK1 to CLK0
00
f1SIO or f2SIO
01
f8SIO
10
f32SIO
CKPOL
CLK
polarity
CLK1
reversing
circuit
Clock output
CTS1 / RTS1/
pin select
CTS0 / CLKS1
n1: Values set to the U1BRG register
PCLK1: Bit in the PCLKR register
SMD2 to SMD0, CKDIR: Bits in U1MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U1C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
Figure 17.2 UART1 Block Diagram
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
RXD polarity reversing
circuit
1/16
CKDIR
U1BRG
Internal
register
0
1 / (n1+1) 1/16
1
External
1/2
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CLKMD0
0
1
CTS/RTS selected
1
CTS/RTS disabled
CRS
1
0
CTS/RTS disabled
CLKMD1 0
0
1
CRD
VSS
Page 178 of 390
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PCLK1
f2SIO
0
1/2
1/2
f1SIO or f2SIO
f1SIO 1
f8SIO
1/8
1/4 f32SIO
UART reception SMD2 to SMD0
010, 100, 101, 110
Reception
Clock synchronous
control circuit
type
001
UART transmission
010, 100, 101, 110
Transmission
Clock synchronous
control circuit
type
001
Clock synchronous type
(when internal clock is selected)
0
1
CKDIR
RTS1
CTS1
0
1
CTS0 from UART0
RCSP
17. Serial Interface
TXD
polarity
reversing
circuit
Transmit/
Receive
receive
clock
unit
Transmit
clock
010-62245566 13810019655
TXD1