Table of Contents
Advertisement
M16C/62P Group (M16C/62P, M16C/62PT)
RXDi
RXD data
reverse circuit
STPS
1SP
0
SP
SP
1
2SP
0
STPS
2SP
1
SP
SP
0
1SP
i=0 to 2
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register
UiERE: Bit in UiC1 register
Figure 17.4
UARTi Transmit/Receive Unit
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
IOPOL
No reverse
0
1
Reverse
PRYE
Clock
synchronous
PAR
type
disabled
0
0
PAR
1
1
PAR enabled
UART
SMD2 to SMD0
0
0
0
0
0
PRYE
UART
SMD2 to SMD0
PAR
(9 bits)
enabled
UART
1
1
PAR
0
0
Clock
PAR
synchronous
disabled
type
Page 180 of 390
提供单片机解密、IC解密、芯片解密业务
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
0
0
1
1
Clock
synchronous type
UART
(9 bits)
UART
(8 bits)
UART
(9 bits)
0
D8
D7 D6
D5 D4 D3
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D8
D7 D6 D5 D4 D3 D2 D1 D0
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
1
1
0
0
UART
UART(7 bits)
(7 bits)
Error signal output
UART
disable
(8 bits)
0
Clock
synchronous type
Error signal
output circuit
1
UiERE
Error signal output
enable
17. Serial Interface
UARTi receive register
D2 D1 D0
UARTi transmit register
IOPOL
No reverse
0
TXD data
reverse circuit
1
Reverse
010-62245566 13810019655
UiRB register
UiTB register
TXDi
Advertisement
Table of Contents
