Renesas M16C/62P Series Hardware Manual page 102

M16C/62P Group (M16C/62P, M16C/62PT)
Peripheral Clock Select Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0
NOTES :
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (w rite enable).
Processor Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (w rite enable).
2. The PM20 bit become effective w hen PLC07 bit in the PLC0 register is set to "1" (PLL on). Change the PM20 bit
w hen the PLC07 bit is set to "0" (PLL off). Set the PM20 bit to "0" (2 w aits) w hen PLL clock > 16MHz.
3. Once this bit is set to "1", it cannot be cleared to "0" in a program.
4. If the PM21 bit is set to "1", w riting to the follow ing bits has no effect:
CM02 bit in CM0 register
CM05 bit in CM0 register (main clock does not stop)
CM07 bit in CM0 register (clock source for the CPU clock does not change)
CM10 bit in CM1 register (stop mode is not entered)
CM11 bit in CM1 register (clock source for the CPU clock does not change)
CM20 bit in CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in PLC0 register (PLL frequency synthesizer settings do not change)
Be aw are that the WAIT instruction cannot be executed w hen the PM21 bit = 1.
5. Setting the PM22 bit to "1" results in the follow ing conditions:
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the w atchdog timer count source.
• The CM10 bit is disabled against w rite. (Writing a "1" has no effect, nor is stop mode entered.)
• The w atchdog timer does not stop w hen in w ait mode or hold state.
Figure 10.5 PCLKR Register and PM2 Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
(1)
Symbol
PCLKR
Bit Symbol
Timers A, B Clock Select Bit
PCLK0
(Clock source for Timers A , B, and the dead timer)
SI/O Clock Select Bit
(Clock source for UART0 to UART2, SI/O3, and
PCLK1
SI/O4)
— Reserved bit
(b7-b2)
(1)
Symbol Address
001Eh
PM2
Bit Symbol Bit Name
Specifying Wait w hen Accessing
PM20
SFR at PLL Operation
System Clock Protective Bit
PM21
WDT Count Source
(3, 5)
Protective Bit
PM22
— Reserved Bit
(b4-b3)
— Nothing is assigned. When w rite, set to "0".
(b7-b5) When read, their contents are indeterminate.
Page 87 of 390
提供单片机解密、IC解密、芯片解密业务
Address
025Eh
Bit Name
0 : 2 w aits
(2)
1 : 1 w aits
(3, 4)
0 : Clock is protected by PRCR register
1 : Clock modification disabled
0 : CPU clock is used for the w atchdog timer
count source
1 : On-chip oscillator clock is used for the
w atchdog timer count source
Set to "0"
10. Clock Generation Circuit
After Reset
00000011b
Function
0 : f2
1 : f1
0 : f2SIO
1 : f1SIO
Set to "0"
After Reset
XXX00000b
Function
010-62245566 13810019655
RW
RW
RW
RW
RW
RW
RW
RW
RW
—