Renesas M16C/62P Series Hardware Manual page 178

M16C/62P Group (M16C/62P, M16C/62PT)
Timer Bi Mode Register (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
1 0
NOTES :
1. This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to "0" (no overflow )
by w riting to the TBiMR register at the next count timing or later after the MR3 bit w as set to "1" (overflow ed). The
MR3 bit cannot be set to "1" in a program. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR
register, and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register.
2. Selected by PCLK0 bit in the PCLKR register.
Figure 15.21 TBiMR Register in Pulse Period and Pulse Width Measurement Mode
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Symbol Address
TB0MR to TB2MR 039Bh to 039Dh
TB3MR to TB5MR 035Bh to 035Dh
Bit Name
Bit Symbol
TMOD0 Operation Mode Select Bit
TMOD1
Measurement Mode Select
Bit
MR0
MR1
TB0MR, TB3MR registers
Set to "0" in pulse period and pulse w idth measurement mode
MR2
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When w rite, set to "0".
When read, its content is indeterminate.
Timer Bi Overflow Flag
MR3
Count Source Select Bit
TCK0
TCK1
Page 163 of 390
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After Reset
00XX0000b
00XX0000b
Function
b1 b0
1 0 : Pulse period / pulse w idth measurement
mode
b3 b2
0 0 : Pulse period measurement
(Measurement betw een a falling edge and
the next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement betw een a rising edge and
the next rising edge of measured pulse)
1 0 : Pulse w idth measurement
(Measurement betw een a falling edge and
the next rising edge of measured pulse
and betw een a rising edge and the next
falling edge)
1 1 : Do not set to this value
(1)
0 : Timer did not overflow
1 : Timer has overflow ed
b7 b6
(2)
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
15. Timers
RW
RW
RW
RW
RW
RW
—
RO
RW
RW
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