Renesas M16C/62P Series Hardware Manual page 220

M16C/62P Group (M16C/62P, M16C/62PT)
17.1.3 Special Mode 1 (I
2
I C mode is provided for use as a simplified I
2
of the I C mode. Table 17.11 to 17.12 lists the registers used in the I
13.13 lists the I
Transfer to UiRB Register and Interrupt Timing.
As shown in Table 17.13, the microcomputer is placed in I
"010b" and the IICM bit to "1". Because SDAi transmit output has a delay circuit attached, SDAi output does
not change state until SCLi goes low and remains stably low.
2
Table 17.10 I C Mode Specifications
Item
Transfer Data Format
Transfer Clock
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
NOTES:
1. When an external clock is selected, the conditions must be met while the external clock is in the high state.
2. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does
not change.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
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2
C mode)
2
C Mode Functions. Figure 17.25 shows the block diagram for I
Transfer data length: 8 bits
• During master
CKDIR bit in the UiMR (i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO
• During slave
CKDIR bit = 1 (external clock) : Input from SCLi pin
Before transmission can start, met the following requirements
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
Before reception can start, met the following requirements
• The RE bit in UiC1 register= 1 (reception enabled)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register= 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
(2)
Overrun error
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 8th bit of the next data
• Arbitration lost
Timing at which the ABT bit in the UiRB register is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
Page 205 of 390
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2
C interface compatible mode. Table 17.10 lists the specifications
2
C mode and the register values set. Table
2
C mode by setting the SMD2 to SMD0 bits to
Specification
n: Setting value of UiBRG register
17. Serial Interface
2
C mode. Figure 17.26 shows
00h to FFh
(1)
(1)
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