Parallel I/O Mode - Renesas M16C/62P Series Hardware Manual

6-bit single-chip microcomputer
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M16C/62P Group (M16C/62P, M16C/62PT)
22.5

Parallel I/O Mode

In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer
supporting the M16C/62P Group (M16C/62P, M16C/62PT). Contact your parallel programmer manufacturer for
more information on the parallel programmer. Refer to the user's manual included with your parallel programmer
for instructions.
22.5.1
User ROM and Boot ROM Areas
An erase block operation in the boot ROM area is applied to only one 4 Kbyte block. The rewrite control
program in standard serial I/O mode is written in the boot ROM area before shipment. Do not rewrite the boot
ROM area if using the serial programmer.
In parallel I/O mode, the boot ROM area is located in addresses 0FF000h to 0FFFFFh. Rewrite this address
range only if rewriting the boot ROM area. (Do not access addresses other than addresses 0FF000h to
0FFFFFh.)
22.5.2
ROM Code Protect Function
The ROM code protect function prevents the flash memory from being read and rewritten in parallel I/O mode.
(Refer to 22.2 Functions To Prevent Flash Memory from Rewriting.)
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Page 303 of 390
提供单片机解密、IC解密、芯片解密业务
22. Flash Memory Version
010-62245566 13810019655

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