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M16C/62P Group (M16C/62P, M16C/62PT)
• Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit)
UiBRG count
source
RE bit in UiC1
register
RXDi
Transfer clock
RI bit in UiC1
register
RTSi
IR bit in SiRIC
register
The above timing diagram applies to the case where the register bits are set as follows:
· PRYE bit in UiMR register = 0 (parity disabled)
· STPS bit in UiMR register = 0 (1 stop bit)
· CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 17.20
Receive Operation
17.1.2.1
Bit Rate
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates. Table
17.9 lists Example of Bit Rates and Settings.
Table 17.9
Example of Bit Rates and Settings
Bit Rate
Count Source
(bps)
of UiBRG
1200
2400
4800
9600
14400
19200
28800
31250
38400
51200
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
"1"
"0"
Start bit
Sampled "L"
Reception triggered when transfer clock
"1"
is generated by falling edge of start bit
"0"
"H"
"L"
"1"
"0"
Peripheral Function Clock : 16MHz
Set Value of
UiBRG : n
f8
103 (67h)
f8
51 (33h)
f8
25 (19h)
f1
103 (67h)
f1
68 (44h)
f1
51 (33h)
f1
34 (22h)
f1
31 (1Fh)
f1
25 (19h)
f1
19 (13h)
Page 201 of 390
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D1
D0
Receive data taken in
Transferred from UARTi receive
register to UiRB register
Set to "0" by an interrupt request acknowledgement or by program
Peripheral Function Clock : 24MHz
Bit Rate (bps)
1202
2404
4808
9615
14493
19231
28571
31250
38462
50000
17. Serial Interface
Stop bit
D7
Set value of
Bit Rate (bps)
UiBRG : n
155 (9Bh)
77 (4Dh)
38 (26h)
155 (9Bh)
103 (67h)
77 (4Dh)
51 (33h)
47 (2Fh)
38 (26h)
28 (1Ch)
010-62245566 13810019655
1202
2404
4808
9615
14423
19231
28846
31250
38462
51724
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