Renesas M16C/62P Series Hardware Manual page 8

12.5 Interrupt Control ......................................................................................111
12.5.1 I Flag.................................................................................................113
12.5.2 IR Bit.................................................................................................113
12.5.3 ILVL2 to ILVL0 Bits and IPL .............................................................113
12.5.4 Interrupt Sequence ...........................................................................114
12.5.5 Interrupt Response Time ..................................................................115
12.5.6 Variation of IPL when Interrupt Request is Accepted .......................115
12.5.7 Saving Registers ..............................................................................116
12.5.8 Returning from an Interrupt Routine .................................................118
12.5.9 Interrupt Priority ................................................................................118
12.5.10 Interrupt Priority Level Select Circuit ................................................119
12.6 INT Interrupt ............................................................................................120
12.7 NMI Interrupt ...........................................................................................121
12.8 Key Input Interrupt...................................................................................121
12.9 Address Match Interrupt ..........................................................................122
13. Watchdog Timer
13.1 Count source protective mode ................................................................125
14. DMAC
14.1 Transfer Cycles .......................................................................................132
14.1.1 Effect of Source and Destination Addresses ....................................132
14.1.2 Effect of BYTE Pin Level ..................................................................132
14.1.3 Effect of Software Wait .....................................................................132
14.1.4 Effect of RDY Signal.........................................................................132
14.2 DMA Transfer Cycles ..............................................................................134
14.3 DMA Enable ............................................................................................135
14.4 DMA Request ..........................................................................................135
14.5 Channel Priority and DMA Transfer Timing.............................................136
15. Timers
15.1 Timer A....................................................................................................139
15.1.1 Timer Mode ......................................................................................144
15.1.2 Event Counter Mode.........................................................................146
15.1.3 One-shot Timer Mode.......................................................................151
15.1.4 Pulse Width Modulation (PWM) Mode..............................................153
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