Renesas M16C/62P Series Hardware Manual page 239

M16C/62P Group (M16C/62P, M16C/62PT)
(1) Transmit Timing
Transfer clock
"1"
TE bit in U2C1
register
"0"
"1"
TI bit in U2C1
register
"0"
TXD2
Parity Error signal
returned from
Receiving end
RXD2 (2)
pin level
"1"
TXEPT bit in U2C0
register
"0"
"1"
IR bit in S2TIC
register
"0"
The above timing diagram applies to the case where data is
transferred in the direct format.
• STPS bit in U2MR register = 0 (1 stop bit)
• PRY bit in U2MR register = 1 (even)
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (no reverse)
• U2IRSCH bit in U2C1 register = 1 (transmit is completed)
(2) Receive Timing
Transfer clock
"1"
RE bit in U2C1
register
"0"
Transmit Waveform
from the
Transmitting end
TXD2
(1)
RXD2 pin level
RI bit in U2C0
"1"
register
"0"
IR bit in S2RIC "1"
register
"0"
The above timing diagram applies to the case where data is
transferred in the direct format.
• STPS bit in U2MR register = 0 (1 stop bit)
• PRY bit in U2MR register = 1 (even)
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (no reverse)
• U2IRSCH bit in U2C1 register = 1 (transmit is completed)
NOTES:
1. Data transmission starts when BRG overflows after a value is set to the U2TB register on the rising edge of the TI bit.
2. Because the TxD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the
TxD2 pin and parity error signal from the receiving end, is generated.
3. Because the TxD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the
transmitting end and parity error signal from the TxD2 pin, is generated.
Figure 17.34 Transmit and Receive Timing in SIM Mode
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Tc
Data is written to the UARTi register
Start
bit
ST D0 D1 D2 D3 D4 D7
D5 D6
ST D0 D3 D7
D1 D2 D4 D5 D6
Tc
Start
bit
ST D7
D0 D1 D2 D3 D4 D5 D6
ST D0 D1 D2 D3 D4 D5 D6 D7
Page 224 of 390
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(Note 1)
Data is transferred from the UiTB
register to the UARi transmit register
Stop
Parity
bit
bit
P ST D0 D1
SP
An "L" signal is applied from the
SIM card due to a parity error
ST D0
P SP D1
An interrupt routine
detects "H" or "L"
Set to "0" by an interrupt request acknowledgement or by program
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Stop
bit
Parity
bit
ST
P SP D0 D1 D2
TxD2 provides "L" output
due to a parity error
P SP ST D0 D1 D2
Read the U2RB register
Set to "0" by an interrupt request acknowledgement or by program
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
17. Serial Interface
D2 D3 D4 D7 P SP
D5 D6
D3 D7 SP
D2 D4 D5 D6 P
An interrupt routine detects "H" or "L"
SP
D7
D3 D4 D5 D6 P
SP
D3 D4 D5 D6 D7 P
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