Renesas M16C/62P Series Hardware Manual page 222

M16C/62P Group (M16C/62P, M16C/62PT)
Table 17.11 Registers to Be Used and Settings in I
Register
(3)
UiTB 0 to 7
(3)
UiRB 0 to 7
8
ABT
OER
UiBRG 0 to 7
(3)
UiMR SMD2 to SMD0
CKDIR
IOPOL
UiC0 CLK1, CLK0
CRS
TXEPT
(4)
CRD
NCH
CKPOL
UFORM
UiC1 TE
TI
RE
RI
(1)
U2IRS
U2RRM
UiLCH, UiERE
UiSMR IICM
ABC
BBS
3 to 7
UiSMR2 IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
7
NOTES:
1. Set the bit 4 and bit 5 in the U0C1 and U1C1 register to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to "0".
3. Not all register bits are described above. Set those bits to "0" when writing to the registers in I
4. When using UART1 in I
U1C0 register to "0" (CTS/RTS enable) and the CRS bit to "0" (CTS input).
i=0 to 2
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
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Bit
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a bit rate
Set to "010b"
Set to "0"
Set to "0"
Select the count source for the UiBRG
register
Invalid because CRD = 1
Transmit buffer empty flag
Set to "1"
(2)
Set to "1"
Set to "0"
Set to "1"
Set this bit to "1" to enable transmission
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
Invalid
(1)
, Set to "0"
Set to "1"
Select the timing at which arbitration-lost
is detected
Bus busy flag
Set to "0"
See Table 17.13 I
Set this bit to "1" to enable clock
synchronization
Set this bit to "1" to have SCLi output fixed
to "L" at the falling edge of the 9th bit of
clock
Set this bit to "1" to have SDAi output
stopped when arbitration-lost is detected
Set to "0"
Set this bit to "1" to have SCLi output
forcibly pulled low
Set this bit to "1" to disable SDAi output
Set to "0"
2
C mode and enabling the CTS/RTS separate function of UART0, set the CRD bit in the
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2
C Mode (1)
Function
Master
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Invalid
Overrun error flag
Invalid
Set to "010b"
Set to "1"
Set to "0"
Invalid
Invalid because CRD = 1
Transmit buffer empty flag
Set to "1"
Set to "1"
Set to "0"
Set to "1"
Set this bit to "1" to enable transmission
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
Invalid
Set to "0"
Set to "1"
Invalid
Bus busy flag
Set to "0"
2
C Mode Functions See Table 17.13 I
Set to "0"
Set this bit to "1" to have SCLi output fixed
to "L" at the falling edge of the 9th bit of
clock
Set to "0"
Set this bit to "1" to initialize UARTi at
start condition detection
Set this bit to "1" to have SCLi output
forcibly pulled low
Set this bit to "1" to disable SDAi output
Set to "0"
17. Serial Interface
Slave
(2)
2
C Mode Functions
2
C mode.
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