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SFR Page Reference
1.
1.1
Applications .................................................................................................1
1.2
Performance Outline ...................................................................................2
1.3
Block Diagram .............................................................................................5
1.4
Product List .................................................................................................7
1.5
Pin Configuration.......................................................................................14
1.6
Pin Description ..........................................................................................25
2.
2.1
Data Registers (R0, R1, R2 and R3).........................................................30
2.2
Address Registers (A0 and A1).................................................................31
2.3
Frame Base Register (FB) ........................................................................31
2.4
Interrupt Table Register (INTB) .................................................................31
2.5
Program Counter (PC) ..............................................................................31
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP).....................31
2.7
Static Base Register (SB)..........................................................................31
2.8
Flag Register (FLG)...................................................................................31
2.8.1
Carry Flag (C Flag).............................................................................31
2.8.2
Debug Flag (D Flag) ...........................................................................31
2.8.3
Zero Flag (Z Flag)...............................................................................31
2.8.4
Sign Flag (S Flag)...............................................................................31
2.8.5
Register Bank Select Flag (B Flag) ....................................................31
2.8.6
Overflow Flag (O Flag) .......................................................................31
2.8.7
Interrupt Enable Flag (I Flag)..............................................................31
2.8.8
Stack Pointer Select Flag (U Flag) .....................................................32
2.8.9
Processor Interrupt Priority Level (IPL) ..............................................32
2.8.10
Reserved Area....................................................................................32
3.
4.
5.
5.1
Hardware Reset 1 .....................................................................................40
5.1.1
Reset on a Stable Supply Voltage......................................................40
5.1.2
Power-on Reset..................................................................................40
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