Renesas M16C/62P Series Hardware Manual page 205

M16C/62P Group (M16C/62P, M16C/62PT)
Table 17.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register
(3)
UiTB 0 to 7
(3)
UiRB 0 to 7
OER
UiBRG 0 to 7
(3)
UiMR SMD2 to SMD0
CKDIR
IOPOL
UiC0 CLK1 to CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1 TE
TI
RE
RI
U2IRS
U2RRM
UiLCH
UiERE
UiSMR 0 to 7
UiSMR2 0 to 7
UiSMR3 0 to 2
NODC
4 to 7
UiSMR4 0 to 7
UCON U0IRS, U1IRS
U0RRM, U1RRM Set this bit to "1" to use continuous receive mode
CLKMD0
CLKMD1
RCSP
7
NOTES:
1. Set the bit 4 and bit 5 in the U0C1 and U1C1 register to "0". The U0IRS, U1IRS, U0RRM and
U1RRM bits in the UCON register.
2. TXD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to "0".
3. Not all register bits are described above. Set those bits to "0" when writing to the registers in clock
synchronous serial I/O mode.
i=0 to 2
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Bit
Set transmission data
Reception data can be read
Overrun error flag
Set a bit rate
Set to "001b"
Select the internal clock or external clock
Set to "0"
Select the count source for the UiBRG register
Select CTS or RTS to use
Transmit register empty flag
Enable or disable the CTS or RTS function
Select TXDi pin output mode
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to "1" to enable transmission/reception
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
(1)
Select the source of UART2 transmit interrupt
(1)
Set this bit to "1" to use continuous receive mode
Set this bit to "1" to use inverted data logic
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Select clock output mode
Set to "0"
Set to "0"
Select the source of UART0/UART1 transmit interrupt
Select the transfer clock output pin when CLKMD1 = 1
Set this bit to "1" to output UART1 transfer clock from two pins
Set this bit to "1" to accept as input the CTS0 signal of the UART0 from
the P6_4 pin
Set to "0"
Page 190 of 390
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17. Serial Interface