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M16C/62P Group (M16C/62P, M16C/62PT)
Memory Expansion Mode, Microprocessor Mode
(
For 3-wait setting, external area access and multiplex bus selection
Read timing
BCLK
CSi
t
d(AD-ALE)
(0.5 × t
ADi
/DBi
t
d(BCLK-AD)
40ns.max
ADi
BHE
(No multiplex)
t
d(BCLK-ALE)
40ns.max
ALE
RD
Write timing
BCLK
CSi
ADi
/DBi
t
d(AD-ALE)
(0.5 × t
-40)ns.min
cyc
t
d(BCLK-AD)
40ns.max
ADi
BHE
(No multiplex)
t
d(BCLK-ALE)
40ns.max
ALE
WR, WRL
WRH
1
t
=
cyc
f(BCLK)
Measuring conditions
· V
=V
=3V
CC1
CC2
· Input timing voltage : V
· Output timing voltage : V
Figure 23.21
Timing Diagram (9)
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
t
cyc
t
d(BCLK-CS)
40ns.max
-40)ns.min
cyc
t
h(ALE-AD)
(0.5 × t
-15)ns.min
cyc
Address
t
dZ(RD-AD)
t
8ns.max
d(AD-RD)
(2.5 × t
0ns.min
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
40ns.max
t
cyc
t
d(BCLK-CS)
40ns.max
t
d(BCLK-DB)
50ns.max
Address
t
h(BCLK-ALE)
-4ns.min
t
d(AD-WR)
0ns.min
t
d(BCLK-WR)
40ns.max
=0.6V, V
=2.4V
IL
IH
=1.5V, V
=1.5V
OL
OH
Page 345 of 390
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)
t
h(RD-CS)
(0.5 × t
cyc
Data input
t
t
ac3(RD-DB)
su(DB-RD)
-60)ns.max
cyc
50ns.min
(0.5 × t
cyc
Data output
t
d(DB-WR)
(2.5 × t
-50)ns.min
(0.5 × t
cyc
23. Electrical Characteristics
V
=V
CC1
CC2
t
h(BCLK-CS)
-10)ns.min
6ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(RD-AD)
(0.5 × t
-10)ns.min
cyc
t
h(BCLK-RD)
0ns.min
t
h(WR-CS)
t
h(BCLK-CS)
-10)ns.min
4ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
-10)ns.min
cyc
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 × t
-10)ns.min
cyc
t
h(BCLK-WR)
0ns.min
010-62245566 13810019655
=3V
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