Renesas M16C/62P Series Hardware Manual page 157

M16C/62P Group (M16C/62P, M16C/62PT)
One-Shot Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. Make sure the PD7_1 bit in the PD7 register is set to "0" (= input mode).
2. Overflow or underflow .
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. Make sure the port direction bits for the TA1IN to TA4IN pins are set to "0" (= input mode).
2. Overflow or underflow .
Figure 15.6 ONSF, RGSR Registers
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Symbol Address
0382h
ONSF
Bit Symbol Bit Name
TA0OS Timer A0 One-Shot Start Flag
TA1OS Timer A1 One-Shot Start Flag
TA2OS Timer A2 One-Shot Start Flag
TA3OS Timer A3 One-Shot Start Flag
TA4OS
Timer A4 One-Shot Start Flag
Z-Phase Input Enable Bit
TAZIE
Timer A0 Event/Trigger Select
TA0TGL
Bit
TA0TGH
Symbol Address
0383h
TRGSR
Bit Symbol Bit Name
Timer A1 Event/Trigger Select Bit
TA1TGL
TA1TGH
Timer A2 Event/Trigger Select Bit
TA2TGL
TA2TGH
Timer A3 Event/Trigger Select Bit
TA3TGL
TA3TGH
Timer A4 Event/Trigger Select Bit
TA4TGL
TA4TGH
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After Reset
00h
Function
The timer starts counting by setting this bit to "1"
w hile the TMOD1 to TMOD0 bits in the TAiMR
register i = 0 to 4) = 10b (= one-shot timer mode)
and the MR2 bit in the TAiMR register = 0 (=TAiOS
bit enabled). When read, its content is 0".
0 : Z-phase input disabled
1 : Z-phase input enabled
b7 b6
0 0 : Input on TA0IN is selected
(2)
0 1 : TB2 is selected
(2)
1 0 : TA4 is selected
1 1 : TA1 is selected (2)
After Reset
00h
Function
b1 b0
0 0 : Input on TA1IN is selected
(2)
0 1 : TB2 is selected
(2)
1 0 : TA0 is selected
(2)
1 1 : TA2 is selected
b3 b2
0 0 : Input on TA2IN is selected
(2)
0 1 : TB2 is selected
(2)
1 0 : TA1 is selected
(2)
1 1 : TA3 is selected
b5 b4
0 0 : Input on TA3IN is selected
(2)
0 1 : TB2 is selected
(2)
1 0 : TA2 is selected
(2)
1 1 : TA4 is selected
b7 b6
0 0 : Input on TA4IN is selected
(2)
0 1 : TB2 is selected
(2)
1 0 : TA3 is selected
(2)
1 1 : TA0 is selected
15. Timers
RW
RW
RW
RW
RW
RW
RW
RW
(1)
RW
RW
RW
(1)
RW
RW
(1)
RW
RW
(1)
RW
RW
(1)
RW
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