Renesas M16C/62P Series Hardware Manual page 251

M16C/62P Group (M16C/62P, M16C/62PT)
A/D Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
NOTES :
If the ADCON2 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
1.
2. If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. The ØAD frequency must be 12 MHz or less. The selected ØAD frequency is determined by a combination of the CKS0
bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register.
CKS2
0
0
0
0
1
1
1
1
Figure 18.3 ADCON2 Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
(1)
Symbol Address
03D4h
ADCON2
Bit Name
Bit Symbol
A/D Conversion Method Select
SMP
Bit
A/D Input Group Select Bit
ADGSEL0
ADGSEL1
— Reserved Bit
(b3)
Frequency Select Bit 2
CKS2
— Nothing is assigned.
(b7-b5) When w rite, set to "0". When read, their contents are "0".
CKS1 CKS0
0 0 Divide-by-4 of fAD
0 1 Divide-by-2 of fAD
1 0 fAD
1 1
0 0 Ddivide-by-12 of fAD
0 1 Divide-by-6 of fAD
1 0 Divide-by-3 of fAD
1 1
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After Reset
0 : Without sample and hold
1 : With sample and hold
b2 b1
0 0 : Port P10 group is selected
0 1 : Do not set
1 0 : Port P0 group is selected
1 1 : Port P2 group is selected
Set to "0"
(3)
0: Selects fAD, fAD divided by 2, or fAD
divided by 4.
1: Selects fAD divided by 3, fAD divided
by 6, or fAD divided by 12.
ØAD
18. A/D Converter
00h
Function
(2)
010-62245566 13810019655
RW
RW
RW
RW
RW
RW
—