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M16C/62P Group (M16C/62P, M16C/62PT)
UARTi Transmit/Receive Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1.
Set the corresponding port direction bit for each CLKi pin to "0" (input mode).
2.
To receive data, set the corresponding port direction bit for each RXDi pin to "0" (input mode).
3.
Set the corresponding port direction bit for SCL and SDA pins to "0" (input mode).
Figure 17.7
UiMR Register
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Symbol
Address
03A0h, 03A8h, 0378h
U0MR to U2MR
Bit Symbol
Bit Name
Serial I/O Mode Select Bit
SMD0
SMD1
SMD2
Internal/External Clock Select
CKDIR
Bit
Stop Bit Length Select Bit
STPS
Odd/Even Parity Select Bit
PRY
Parity Enable Bit
PRYE
TXD, RXD I/O Polarity Reverse
IOPOL
Bit
Page 183 of 390
提供单片机解密、IC解密、芯片解密业务
After Reset
Function
(2)
b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
2
(3)
0 1 0 : I
C mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Do not set except above
0 : Internal clock
(1)
1 : External clock
0 : 1 stop bit
1 : 2 stop bits
Effective w hen PRYE = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
17. Serial Interface
00h
010-62245566 13810019655
RW
RW
RW
RW
RW
RW
RW
RW
RW
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