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M16C/62P Group (M16C/62P, M16C/62PT)
Main clock, PLL clock, or on-chip oscillator clock
(UART2)
RXD2
Clock source selection
CLK1 to CLK0
00
f1SIO or f2SIO
01
f8SIO
10
f32SIO
CKPOL
CLK
polarity
CLK2
reversing
circuit
CTS/RTS selected
CTS2 /
RTS2
CRS
n2: Values set to the U2BRG register
PCLK1: Bit in PCLKR register
SMD2 to SMD0, CKDIR: Bits in U2MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
NOTES :
1. UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
Figure 17.3
UART2 Block Diagram
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
RXD polarity reversing
circuit
1/16
CKDIR
U2BRG
Internal
register
0
1 / (n2+1)
1/16
1
External
1/2
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CTS/RTS disabled
1
CTS/RTS disabled
0
0
1
CRD
VSS
Page 179 of 390
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PCLK1
f2SIO
0
1/2
1/2
1
f1SIO
1/8
1/4
UART reception
SMD2 to SMD0
010, 100, 101, 110
Reception
Clock synchronous
control circuit
type
001
UART transmission
Transmission
010, 100, 101, 110
control circuit
Clock synchronous
type
001
Clock synchronous type
(when internal clock is selected)
0
1
CKDIR
RTS2
CTS2
17. Serial Interface
f1SIO or f2SIO
f8SIO
f32SIO
TXD
polarity
reversing
circuit
Transmit/
receive
Receive
unit
clock
Transmit
clock
010-62245566 13810019655
TXD2
(1)
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