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M16C/62P Group (M16C/62P, M16C/62PT)
Chip Select Control Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
_____
Where the RDY
1.
(w ith w ait state).
2.
If the PM17 bit in the PM1 register is set to "1" (w ith w ait state), set the CSiW bit to "0" (w ith w ait state).
3.
When the CSiW bit = 0 (w ith w ait state), the number of w ait states can be selected using the CSEi1W to CSEi0W bits
in the CSE register.
Figure 8.1
CSR Register
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Symbol
CSR
Bit Name
Bit Symbol
____
CS0
Output Enable Bit
CS0
____
CS1
Output Enable Bit
CS1
____
CS2
Output Enable Bit
CS2
____
CS3
Output Enable Bit
CS3
____
CS0
Wait Bit
CS0W
____
CS1
Wait Bit
CS1W
____
CS2
Wait Bit
CS2W
____
CS3
Wait Bit
CS3W
signal is used in the area indicated by CSi
Page 61 of 390
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Address
0008h
0 : Chip select output disabled
(functions as I/O port)
1 : Chip select output enabled
0 : With w ait state
1 : Without w ait state
____
(i = 0 to 3) or the multiplex bus is used, set the CSiW bit to
After Reset
00000001b
Function
(1, 2, 3)
010-62245566 13810019655
8. Bus
RW
RW
RW
RW
RW
RW
RW
RW
RW
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