Renesas M16C/62P Series Hardware Manual page 232

M16C/62P Group (M16C/62P, M16C/62PT)
Table 17.16 Registers to Be Used and Settings in Special Mode 2
Register
(3)
UiTB 0 to 7
(3)
UiRB 0 to 7
OER
UiBRG 0 to 7
(3)
UiMR SMD2 to SMD0
CKDIR
IOPOL
UiC0 CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1 TE
TI
RE
RI
U2IRS
U2RRM
UiERE
UiSMR 0 to 7
UiSMR2 0 to 7
UiSMR3 CKPH
NODC
0, 2, 4 to 7
UiSMR4 0 to 7
UCON U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7 Set to "0"
NOTES:
1. Set the bit 4 and bit 5 in the U0C0 and U1C1 register to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to "0".
3. Not all register bits are described above. Set those bits to "0" when writing to the registers in Special Mode 2.
i = 0 to 2
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Bit
Set transmission data
Reception data can be read
Overrun error flag
Set a bit rate
Set to "001b"
Set this bit to "0" for master mode or "1" for slave mode
Set to "0"
Select the count source for the UiBRG register
Invalid because CRD = 1
Transmit register empty flag
Set to "1"
Select TXDi pin output format
Clock phases can be set in combination with the CKPH bit in the UiSMR3 register
Set to "0"
Set this bit to "1" to enable transmission
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
(1)
Select UART2 transmit interrupt factor
(1)
, UiLCH, Set to "0"
Set to "0"
Set to "0"
Clock phases can be set in combination with the CKPOL bit in the UiC0 register
Set to "0"
Set to "0"
Set to "0"
Select UART0 and UART1 transmit interrupt factor
Set to "0"
Invalid because CLKMD1 = 0
Page 217 of 390
提供单片机解密、IC解密、芯片解密业务
Function
(2)
010-62245566 13810019655
17. Serial Interface