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M16C/62P Group (M16C/62P, M16C/62PT)
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
CSi
ADi
BHE
ALE
RD
DBi
Write timing
BCLK
CSi
ADi
BHE
ALE
WR,WRL,
WRH
DBi
1
t
=
cyc
f(BCLK)
Measuring conditions
· V
=V
=3V
CC1
CC2
· Input timing voltage : V
· Output timing voltage : V
Figure 23.17
Timing Diagram (5)
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
t
d(BCLK−CS)
30ns.max
t
cyc
t
d(BCLK−AD)
30ns.max
t
t
h(BCLK−ALE)
d(BCLK−ALE)
−4ns.min
30ns.max
t
d(BCLK−RD)
30ns.max
t
(1.5 × t
Hi−Z
t
d(BCLK−CS)
30ns.max
t
cyc
t
d(BCLK−AD)
30ns.max
t
t
d(BCLK−ALE)
h(BCLK−ALE)
−4ns.min
30ns.max
t
d(BCLK−WR)
Hi−Z
(0.5 × t
=0.6V, V
=2.4V
IL
IH
=1.5V, V
=1.5V
OL
OH
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t
h(BCLK−CS)
4ns.min
t
h(BCLK−AD)
4ns.min
t
h(RD−AD)
0ns.min
t
h(BCLK−RD)
0ns.min
ac2(RD−DB)
−60)ns.max
cyc
t
su(DB−RD)
50ns.min
t
h(BCLK−CS)
4ns.min
t
h(BCLK−AD)
t
h(WR−AD)
(0.5 × t
−10)ns.min
cyc
t
h(BCLK−WR)
30ns.max
0ns.min
t
t
d(BCLK−DB)
h(BCLK−DB)
40ns.max
4ns.min
t
t
d(DB−WR)
h(WR−DB)
−40)ns.min
(0.5 × t
−10)ns.min
cyc
cyc
23. Electrical Characteristics
V
=V
CC1
CC2
t
h(RD−DB)
0ns.min
4ns.min
010-62245566 13810019655
=3V
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