Renesas M16C/62P Series Hardware Manual page 215

M16C/62P Group (M16C/62P, M16C/62PT)
(1) 8-bit Data Transmit Timing (with a parity and 1 stop bit)
Transfer Clock
"1"
TE bit in UiC1
register
"0"
"1"
TI bit in UiC1
register
"0"
"H"
CTSi
"L"
TXDi
"1"
TXEPT bit in UiC0
register
"0"
"1"
IR bit in
SiTIC register
"0"
i=0 to 2
The above timing diagram applies to the case where the register bits are set
as follows:
· PRYE bit in UiMR register = 1 (parity enabled)
· STPS bit in UiMR register = 0 (1 stop bit)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled) and
CRS bit = 0 (CTS selected)
· UiIRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
(1) 9-bit Data Transmit Timing (with no parity and 2 stop bits)
Transfer Clock
"1"
TE bit in UiC1
register
"0"
"1"
TI bit in UiC1
register
"0"
TXDi
"1"
TXEPT bit in
UiC0 register
"0"
"1"
IR bit in
SiTIC register
"0"
i=0 to 2
The above timing diagram applies to the case where the register bits are set
as follows:
· PRYE bit in UiMR register = 0 (parity disabled)
· STPS bit in UiMR register = 1 (2 stop bits)
· CRD bit in UiC0 register = 1 (CTS/RTS disabled)
· UiIRS bit = 0 (an interrupt request occurs when transmit
buffer becomes empty):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
Figure 17.19 Transmit Operation
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
The transfer clock stops momentarily, because an "H" single is applied to the CTS pin,
when the stop bit is verified.
Tc
The transfer clock resumes running as soon as an "L" single is applied to the CTS pin.
Data is set in the UiTB register
Start bit
ST D0 D1 D2 D3 D4 D5 D6
Tc
Data is set in the UiTB register
Data is transferred from the UiTB register to the UARTi transmit register
Start bit
ST D0 D1 D2 D3 D4 D5 D6 D7
Set to "0" by an interrupt request acknowledgement or by program
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Data is transferred from the UiTB register to
the UARTi transmit register
Stop
Parity
bit
bit
D7 P SP ST D0 D1 D2 D3
Set to "0" by an interrupt request acknowledgement or by program
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
Stop
Stop
bit bit
D8 SP SP ST D0 D1 D2 D3
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
17. Serial Interface
Pulse stops because the TE bit is set to "0"
ST
D4 D5 D6 D7 P SP
D4 D5 D6 D7 D8 SP SP ST
010-62245566 13810019655
D0 D1
D0 D1