Int Interrupt - Renesas M16C/62P Series Hardware Manual

M16C/62P Group (M16C/62P, M16C/62PT)
12.6

INT Interrupt

INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi
bit in the IFSR register.
INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively. To use
the INT4 interrupt, set the IFSR6 bit in the IFSR register to "1" (= INT4). To use the INT5 interrupt, set the IFSR7
bit in the IFSR register to "1" (= INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to "0" (= interrupt not requested) before
enabling the interrupt.
Figure 12.11 shows the IFSR and IFSR2A Registers.
Interrupt Factor Select Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. When setting this bit to "1" (= both edges), make sure the POL bit in the INT0IC to INT5IC register are set to "0"
(= falling edge).
2. During memory expansion and microprocessor modes, w hen the data bus is 16 bits w ide (BYTE pin is "L"), set
this bit to "0" (= SI/O3, SI/O4).
3. When setting this bit to "0" (= SI/O3, SI/O4), make sure the POL bit in the S3IC and S4IC registers are set to "0"
(= falling edge).
Interrupt Factor Select Register 2
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. Timer B3 and UART0 bus collision detection share the vector and interrupt control register. When using Timer B3
interrupt, clear the IFSR26 bit to "0" (Timer B3). When using UART0 bus collision detection, set the IFSR26 bit to "1".
2. Timer B4 and UART1 bus collision detection share the vector and interrupt control register. When using Timer B4
interrupt, clear the IFSR27 bit to "0" (Timer B4). When using UART1 bus collision detection, set the IFSR27 bit to "1".
Figure 12.11 IFSR and IFSR2A Registers
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Address
Symbol
IFSR
Bit Symbol Bit Name
INT0 Interrupt Polarity Sw itching Bit
IFSR0
INT1 Interrupt Polarity Sw itching Bit
IFSR1
INT2 Interrupt Polarity Sw itching Bit
IFSR2
INT3 Interrupt Polarity Sw itching Bit
IFSR3
INT4 Interrupt Polarity Sw itching Bit
IFSR4
INT5 Interrupt Polarity Sw itching Bit
IFSR5
Interrupt Request Factor Select Bit
IFSR6
Interrupt Request Factor Select Bit
IFSR7
Symbol Address
035Eh
IFSR2A
Bit Symbol Bit Name
— Nothing is assigned. When w rite, set to "0".
(b5-b0) When read, their contents are indeterminate.
Interrupt Request Factor Select Bit
IFSR26
Interrupt Request Factor Select Bit
IFSR27
Page 120 of 390
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035Fh
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
(2)
0 : SI/O3
_____
1 : INT4
(2)
0 : SI/O4
_____
1 : INT5
(1)
0 : Timer B3
1 : UART0 bus collision detection
(2)
0 : Timer B4
1 : UART1 bus collision detection
After Reset
00h
Function
(1)
(1)
(1)
(1)
(1)
(1)
(3)
(3)
After Reset
00XXXXXXb
Function
010-62245566 13810019655
12. Interrupt
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
RW
RW