Renesas M16C/62P Series Hardware Manual page 164

M16C/62P Group (M16C/62P, M16C/62PT)
Timer A2 Mode Register (i=2 to 4)
(when using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 0 1
NOTES :
1. TCK1 bit is valid for Timer A3 mode register. No matter how this bit is set, Timer A2 and A4 alw ays operate in normal
processing mode and x4 processing mode, respectively.
2. If tw o-phase pulse signal processing is desired, follow ing register settings are required:
• Set the TAiP bit in the UDF register to "1" (tw o-phase pulse signal processing function enabled).
• Set the TAiTGH and TAiTGL bits in the TRGSR register to "00b" (TAiIN pin input).
• Set the port direction bits for TAiIN and TAiOUT to "0" (input mode).
Figure 15.10 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse
signal processing with Timer A2, A3 and A4)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Symbol
TA2MR to TA4MR
Bit Name
Bit Symbol
Operation Mode Select Bit
TMOD0
TMOD1
To use tw o-phase pulse signal processing, set this bit to "0".
MR0
To use tw o-phase pulse signal processing, set this bit to "0".
MR1
To use tw o-phase pulse signal processing, set this bit to "1".
MR2
To use tw o-phase pulse signal processing, set this bit to "0".
MR3
Count Operation Type Select Bit
TCK0
Tw o-phase pulse signal processing
TCK1
Operation Type Select Bit
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Address
0398h to 039Ah
b1 b0
0 1 : Event counter mode
0 : Reload type
1 : Free-run type
0 : Normal processing operation
(1, 2)
1 : Multiply-by-4 processing operation
15. Timers
After Reset
00h
Function
010-62245566 13810019655
RW
RW
RW
RW
RW
RW
RW
RW
RW