Renesas M16C/62P Series Hardware Manual page 199

M16C/62P Group (M16C/62P, M16C/62PT)
UARTi Transmit/Receive Control Register 0 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1. Set the corresponding port direction bit for each CLKi
2.
TXD2/SDA2 and SCL2 are N-channel open-drain output. Cannot be set to the CMOS output. No NCH bit in U2C0
register is assigned. When w rite, set to "0".
3. The UFORM bit is enabled w hen the SMD2 to SMD0 bits in the UiMR register are set to "001b" (clock synchronous
serial I/O mode), or "101b" (UART mode, 8-bit transfer data).
Set this bit to "1" w hen the SMD2 to SMD0 bits are set to "010b" (I
are set to "100b" (UART mode, 7-bit transfer data) or "110b" (UART mode, 9-bit transfer data).
______ ______
4.
CTS1 /RTS1 can be used w hen the CLKMD1 bit in the UCON register = 0 (only CLK1 output) and the RCSP
bit in the UCON register = 0 (CTS0
5. Selected by PCLK1 bit in the PCLKR register.
6. When changing the CLK1 to CLK0 bits, set the UiBRG register.
Figure 17.8 UiC0 Register
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Symbol Address
03A4h, 03ACh, 037Ch
U0C0 to U2C0
Bit Name
Bit Symbol
UiBRG Count Source
CLK0
(6)
Select Bit
CLK1
_____ _____
CTS/ RTS Function
(4)
Select Bit
CRS
Transmit Register Empty
Flag
TXEPT
_____ _____
CTS/ RTS Disable Bit
CRD
Data Output Select Bit
NCH
CLK Polarity Select Bit
CKPOL
Transfer Format Select
UFORM
(3)
Bit
______ ______
/RTS0 not separated).
Page 184 of 390
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b1 b0
0 0 : f1SIO or f2SIO is selected
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Do not set to this value
Effective w hen CRD = 0
_____
0 : CTS function is selected
_____
1 : RTS function is selected
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
_____ ____
0 : CTS/ RTS function enabled
____ ____
1 : CTS /RTS function disabled
(P6_0, P6_4 and P7_3 can be used as I/O ports)
(2)
0 : TXDi/SDAi and SCLi pins are CMOS output
1 : TXDi/SDAi and SCLi pins are N-channel
open-drain output
0 : Transmit data is output at falling edge of transfer
clock and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer
clock and receive data is input at falling edge
0 : LSB first
1 : MSB first
______
pin to "0" (input mode).
2
C mode), and to "0" w hen the SMD2 to SMD0 bits
17. Serial Interface
After Reset
00001000b
Function
(5)
(1)
010-62245566 13810019655
RW
RW
RW
RW
RO
RW
RW
RW
RW