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M16C/62P Group (M16C/62P, M16C/62PT)
CM10=1(stop mode)
WAIT instruction
RESET
Software reset
NMI
Interrupt request level judgment output
CM02, CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM11, CM16, CM17: Bits in CM1 register
PCLK0, PCLK1: Bits in PCLKR register
CM21, CM27
: Bits in CM2 register
Main
clock
Main clock
Figure 10.1
Clock Generation Circuit
Rev.2.41
Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Sub-clock
generating circuit
XCIN
XCOUT
CM04
CM21
Q
S
XIN
XOUT
R
Main
clock
Main clock
generating circuit
CM05
S
Q
R
Oscillation Stop, Re-Oscillation Detection Circuit
Pulse generation
circuit for clock
Charge,
edge detection
discharge
and charge,
circuit
discharge control
PLL Frequency Synthesizer
Programmable
counter
Phase
compar
ator
Page 83 of 390
提供单片机解密、IC解密、芯片解密业务
I/O ports
PM01 to PM00=00b, CM01 to CM00=01b
PM01 to PM00=00b, CM01 to CM00=10b
Sub-clock
fC
On-chip
On-chip
oscillator
oscillator
clock
Oscillation
stop,
re-oscillation
detection
circuit
PLL
frequency
synthesizer
PLL
CM21=1
clock
1
0
CM21=0
CM11
CM02
e
1/2
1/2
a
1/2
1/4
CM06=0
CM17 to CM16=10b
CM06=0
CM17 to CM16=01b
CM06=0
CM17 to CM16=00b
Reset
CM27=0
generating
Oscillation stop
circuit
detection reset
Oscillation stop,
re-oscillation
CM27=1
detection interrupt
generating circuit
CM21 switch signal
Charge
pump
oscillator
Internal lowpass
10. Clock Generation Circuit
CM01 to CM00=00b
PM01 to PM00=00b,
CM01 to CM00=11b
fC32
1/32
f1
PCLK0=1
f2
PCLK0=0
f8
f32
fAD
f1SIO
PCLK1=1
f2SIO
PCLK1=0
f8SIO
f32SIO
e
b
c
CM07
0
a
=
d
Divider
fC
CM07
1
=
b
1/2
1/2
1/2
1/8
1/16
CM06=0
CM17 to CM16=11b
CM06=1
Details of divider
Oscillation stop
detection reset
1/2
PLL Clock
Voltage
control
(VCO)
filter
010-62245566 13810019655
CLKOUT
D4INT clock
CPU clock
BCLK
c
1/32
d
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