Renesas M16C/62P Series Hardware Manual page 65

M16C/62P Group (M16C/62P, M16C/62PT)
Low Voltage detection Circuit
VC27
VCC1 +
Noise
Rejection
VREF
-
(Rejection Range : 200 ns)
The Low Voltage detection signal
becomes "H" when the VC27 bit is
set to "0" (disabled)
WAIT instruction (wait mode)
Watchdog Timer Block
Watchdog timer
underflow signal
Figure 6.5 Low Voltage detection Interrupt Generation Block
VCC1
VC13 bit in VCR1 register
(2)
Output of the digital filter
D42 bit in D4INT register
Low Voltage detection
interrupt signal
NOTES :
1. D40 bit in the D4INT register is set to "1" (low voltage detection interrupt enabled).
2. Output of the digital filter is shown in Figure 6.5.
Figure 6.6 Low Voltage Detection Interrupt Generation Circuit Operation Example
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Low Voltage detection interrupt generation circuit
D4INT clock (the
1/8 1/2 1/2
clock with which it
operates also in
wait mode)
VC13
Noise Rejection
Circuit
Low Voltage
detection signal
CM10
CM02
D43
This bit is set to "0" (not detected) by program.
sampling
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DF1, DF0
00b
The D42 bit is set to "0" (not detected)
01b by program. The VC27 bit is set to "0"
(voltage down detect circuit disabled),
10b
the D42 bit is set to "0".
11b
1/2
D42
Digital
Filter
D41
D40
sampling sampling
No low voltage detection interrupt signals are
generated when the D42 bit is "H".
Set to "0" by program (not detected)
6. Voltage Detection Circuit
Watchdog
timer interrupt
signal
Low Voltage
interrupt
detection
Non-maskable
signal
interrupt signal
Oscillation stop,
re-oscillation
detection
interrupt signal
sampling
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