Renesas M16C/62P Series Hardware Manual page 289

M16C/62P Group (M16C/62P, M16C/62PT)
ROM Code Protect Control Address
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1 1 1
NOTES :
1. When the ROM code protection is active by the ROMCP1 bit setting, the flash memory is protected against reading or
rew riting in parallel I/O mode.
2. Set the bit 5 to bit 0 to "111111b" w hen the ROMCP1 bit is set to a value other than "11b".
If the bit 5 to bit 0 are set to values other than "111111b", the ROM code protection may not become active by setting
the ROMCP1 bit to a value other than "11b".
3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard serial I/O mode
or CPU rew rite mode.
4. The ROMCP address is set to "FFh" w hen a block, including the ROMCP address, is erased.
When a value of the ROMCP address is "00h" or "FFh", the ROM code protect function is disabled.
5.
Figure 22.2 ROMCP Register
Figure 22.3 Address for ID Code Stored
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
(5)
Symbol Address
0FFFFFh
ROMCP
Bit Symbol Bit Name
— Reserved Bit
(b5-b0)
ROM Code Protect Level 1 Set
(1, 2, 3, 4)
Bit
ROMCP1
Address
0FFFDFh to 0FFFDCh
0FFFE3h to 0FFFE0h
0FFFE7h to 0FFFE4h
0FFFEBh to 0FFFE8h
0FFFEFh to 0FFFECh
0FFFF3h to 0FFFF0h
0FFFF7h to 0FFFF4h
0FFFFBh to 0FFFF8h
0FFFFFh to 0FFFFCh
Page 274 of 390
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Set to "1"
b7 b6
0 0 :
0 1 : ROM code protection active
1 0 :
1 1 : ROM code protection inactive
Undefined instruction vector
ID1
ID2 Overflow vector
BRK instruction vector
ID3 Address match vector
ID4 Single step vector
ID5 Watchdog timer vector
ID6 DBC vector
ID7 NMI vector
Reset vector
ROMCP
4 bytes
22. Flash Memory Version
Factory Setting
(4)
FFh
Function
010-62245566 13810019655
RW
RW
RW