Renesas M16C/62P Series Hardware Manual page 84

M16C/62P Group (M16C/62P, M16C/62PT)
Table 8.8 Bit and Bus Cycle Related to Software Wait
Area Bus Mode
−
SFR
−
−
Internal
−
RAM,
ROM
External Separate
Area Bus
Multiplexed
(2)
Bus
NOTES:
1. To use the RDY signal, set this bit to "0".
2. To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to "0" (with wait
state).
3. When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by
the PM20 bit in the PM2 register. When using a 16 MHz or higher PLL clock, be sure to set the
PM20 bit to "0" (2 wait cycles).
4. After reset, the PM17 bit is set to "0" (without wait state), all of the CS0W to CS3W bits are set to "0"
(with wait state), and the CSE register is set to "00h" (one wait state for CS0 to CS3). Therefore, the
internal RAM and internal ROM are accessed with no wait states, and all external areas are
accessed with one wait state.
5. When PM17 bit is set to "1" and accesses an external area, set the CSiW (i=0 to 3) bits to "0" (with
wait state).
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
CSR Register
PM2 PM1 CS3W Bit
Register Register CS2W Bit
(5)
PM20 Bit PM17 Bit CS1W Bit
CS0W Bit
−
1
−
0
−
0
−
1
−
0
− −
− −
− −
−
1
− −
− −
− −
−
1
Page 69 of 390
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CSE Register
(1)
CSE31W to CSE30W Bit
(1)
CSE21W to CSE20W Bit
(1)
CSE11W to CSE10W Bit
(1)
CSE01W to CSE00W Bit
− −
− −
− −
− −
1 00b
0 00b
0 01b
0 10b
0 00b
0 00b
0 01b
0 10b
0 00b
8. Bus
Software
Bus Cycle
Wait
−
(3)
2 BCLK cycles
−
(3)
3 BCLK cycles
(4)
No wait 1 BCLK cycle
1 wait 2 BCLK cycles
No wait 1 BCLK cycle
(read)
2 BCLK cycles
(write)
(4)
1 wait 2 BCLK cycle
2 waits 3 BCLK cycles
3 waits 4 BCLK cycle
1 wait 2 BCLK cycle
1 wait 3 BCLK cycles
2 waits 3 BCLK cycles
3 waits 4 BCLK cycles
1 wait 3 BCLK cycles
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