Renesas M16C/62P Series Hardware Manual page 127

M16C/62P Group (M16C/62P, M16C/62PT)
INTi (0 to 5) Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
NOTES :
1. This bit can only be reset by w riting "0" (Do not w rite "1").
2. To rew rite the interrupt control register, do so at a point that does not generate the interrupt request for that register.
For details, refer to 24.6 Interrupt.
3. If the IFSRi bit (i = 0 to 5) in the IFSR register are "1" (both edges), set the POL bit in the INTiIC register to "0" (falling
edge).
4. When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the LVL2 to
ILVL0
5. Set the POL bit in the S3IC or S4IC register to "0" (falling edge) w hen the IFSR6 bit in the IFSR register = 0 (SI/O3
selected) or IFSR7 bit = 0 (SI/O4 selected), respectively.
Figure 12.4 Interrupt Control Registers (2)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
(2)
Symbol
(4)
INT3IC
S4IC/INT5IC
S3IC/INT4IC
005Dh to 005Fh
INT0IC to INT2IC
Bit Name
Bit Symbol
Interrupt Priority Level Select Bit
ILVL0
ILVL1
ILVL2
Interrupt Request Bit
IR
Polarity Select Bit
POL
— Reserved Bit
(b5)
— Nothing is assigned. When w rite, set to "0".
(b7-b6) When read, their contents are indeterminate.
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Address
0044h
0048h
0049h
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Set to "0"
12. Interrupt
After Reset
XX00X000b
XX00X000b
XX00X000b
XX00X000b
Function
RW
(3, 5)
010-62245566 13810019655
RW
RW
RW
RW
(1)
RW
RW
—