Renesas M16C/62P Series Hardware Manual page 337

M16C/62P Group (M16C/62P, M16C/62PT)
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
(Common to setting with wait and setting without wait)
BCLK
HOLD input
HLDA input
P0, P1, P2,
P3, P4,
P5_0 to P5_2
(1)
NOTES:
1. These pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.
Measuring conditions :
·
V
·
CC1
Input timing voltage : Determined with V
·
Output timing voltage : Determined with V
·
Figure 23.5 Timing Diagram (3)
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
t
su(HOLD−BCLK)
t
d(BCLK−HLDA)
=V =5V
CC2
Page 322 of 390
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t
su(RDY−BCLK)
t
h(BCLK−HOLD)
t
d(BCLK−HLDA)
−
Hi Z
=1.0V, V
IL
=2.5V, V
OL
23. Electrical Characteristics
V =V
CC1 CC2
t
h(BCLK−RDY)
=4.0V
IH
=2.5V
OH
010-62245566 13810019655
=5V