Renesas M16C/62P Series Hardware Manual page 236

M16C/62P Group (M16C/62P, M16C/62PT)
(1) The ABSCS Bit in the UiSMR Register (Bus collision detect sampling clock select)
Transfer clock
TXDi
RXDi
Timer Aj
Timer Aj: Timer A3 when UART0; Timer A4 when UART1; Timer A0 when UART2
(2) The ACSE Bit in the UiSMR Register (Auto clear of transmit enable bit)
Transfer clock
TXDi
RXDi
IR bit in UiBCNIC
(1)
register
TE bit in UiC1
register
NOTES :
1. BCNIC register when UART2.
(3) The SSS Bit in the UiSMR Register (Transmit start condition select)
If SSS bit = 0, the serial interface starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
TXDi
Transmission enable condition is met
If SSS bit = 1, the serial interface starts sending data at the rising edge
CLKi
TXDi
RXDi
NOTES :
1. The falling edge of RXDi when IOPOL=0; the rising edge of RXDi when IOPOL =1.
2. The transmit condition must be met before the falling edge
This diagram applies to the case where IOPOL=1 (reversed).
Figure 17.33 Bus Collision Detect Function-Related Bits
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
ST D0 D1
Trigger signal is applied to the TAjIN pin
ST D0 D1
ST D0
ST D0
(NOTE 2)
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D2 D3 D4 D5
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
D2 D3 D4 D5
D1 D2 D3 D4 D5
(1)
of RXDi
D1 D2 D3 D4 D5
(1)
of RXD.
17. Serial Interface
(i=0 to 2)
D6 D7 D8 SP
D6 D7 D8 SP
If ACSE bit = 1 (automatically
clear when bus collision occurs), the
TE bit is cleared to "0"
(transmission disabled) when the
IR bit in the UiBCNIC register= 1
(unmatching detected).
D6 D7 D8 SP
D6 D7 D8 SP
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