Renesas M16C/62P Series Hardware Manual page 176

M16C/62P Group (M16C/62P, M16C/62PT)
.
Timer Bi Mode Register (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
0 1
NOTES :
1. Effective w hen the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow ), these bits can
be set to "0" or "1".
2. The port direction bit for the TBiIN pin must be set to "0" (= input mode).
Figure 15.20 TBiMR Register in Event Counter Mode
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Symbol
TB0MR to TB2MR 039Bh to 039Dh
TB3MR to TB5MR 035Bh to 035Dh
Bit Name
Bit Symbol
TMOD0 Operation Mode Select Bit
TMOD1
Count Polarity Select Bit
MR0
MR1
TB0MR, TB3MR registers
Set to "0" in event counter mode
MR2
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When w rite, set to "0".
When read, its content is indeterminate.
When w rite in event counter mode, set to "0".
MR3
When read in event counter mode, its content is indeterminate.
Has no effect in event counter mode.
TCK0
Can be set to "0" or "1".
Event Clock Select
TCK1
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Address
b1 b0
0 1 : Event counter mode
(1)
b3 b2
0 0 : Counts falling edges of external signal
0 1 : Counts rising edges of external signal
1 0 : Counts falling and rising edges
external signal
1 1 : Do not set to this value
0 : Input from TBiIN pin
1 : TBj overflow or underflow
(j = i – 1, how ever, j = 2 if i = 0,
After Reset
00XX0000b
00XX0000b
Function
(2)
j = 5 if i = 3)
010-62245566 13810019655
15. Timers
RW
RW
RW
RW
RW
RW
—
RO
RW
RW