Table 31. Had Header For Mdc Interposer (J9E4); Table 32.Had Header For Mdc Interposer (J9E7) - Intel ® Core i7 User Manual

4.6.2.6

Table 31. HAD Header for MDC Interposer (J9E4)

Table 32.HAD Header for MDC Interposer (J9E7)

Dev Kit Manual
Pin
8 PCH_GPIO24_PWR_EN#
HAD Header for MDC Interposer
Pin
1 GND
2 HDA_MDC_SDATAIN2
3 +V3.3
4 HDA_MDC_SDATAIN23
5 N/C
6 HDA_MDC_SDATAIN21
7 VBATS_HDA_R1
8 HDA_MDC_SDATAIN20
9 +V3.3
10 HDA_MDC_SDO
11 GND
12 HDA_MDC_SYNC
13 V3.3A_1.5A_HDA_IO
14 HDA_MDC_RST#
15 GND
16 HDA_MDC_BITCLK
Pin
1 HDA_AUDIO_PWRDN_NET
2 HDA_SPKR_R
3 GND
4 +V5
5 +V3.3A
6 MEMS_CLK_R
7 HDA_DOCK_RST#_R
8 HDA_DOCK_EN#_R
Signal
Finger Print Power
Enable
Signal
Ground
Data In 2
3.3 volt supply
Data In 3
Reserved
Data In 1
6V – 14.1V supply
Data In 0
3.3 volt supply
Data Out
Ground
Synch
3.3 volt supply
Reset
Ground
Clock
Signal
Pull-down to low
Speaker
Ground
5 volt supply
3.3 volt supply
Clock
Reset (active low)
Dock enable
Definition
Definition
Definition
57 323094