Intel ® Pentium ® M/Celeron ® M Processor Core Power Delivery And Decoupling Concept Example (Option #4); Intel ® Pentium ® M/Celeron ® M Processor Core Power Delivery - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
A conceptual diagram of this V
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Figure 43. Intel Pentium
and Decoupling Concept Example (Option #4)
South/Legacy Side
PKG PKG
SKT SKT
L1 PS L1 PS
L2 GND L2 GND
L3 Sig L3 Sig
L4 GND L4 GND
L5 PWR L5 PWR
L6 Sig L6 Sig
L7 GND L7 GND
L8 SS L8 SS
Signals
Signals
In this example, (option 4) bulk-decoupling 220 µF SP capacitors from V
option 4 are placed on the north side of the secondary side layer in the Intel Pentium M/Celeron M
processor V
CC-CORE
connection) is on the positive terminal side of the 220 µF SP capacitors. Both V
ground vias are used on both sides of the SP capacitors' positive terminal side to reduce the
inductance of the capacitor connection as illustrated by the current flow loop area in
When the VR feed is on the negative side of the SP capacitors, both V
vias are needed on both the positive and negative terminals of the capacitor to reduce the effective
inductance of the capacitor.
Layers 1 (primary side layer), 3, 5, 6, and (secondary side layer) 8 are used for V
feeding while referencing Layers 2, 4, and 7 (ground planes) with a small dielectric separation (see
Figure 2). These layers are solid ground planes in the areas under the Intel Pentium M/Celeron M
processor package outline and where the decoupling capacitors are placed. This results in a
reduction in effective loop inductance. For the recommended layout examples shown in
and Figure 44, a low inductance value of ~41 pH is achieved.
Bulk decoupling capacitors respond too slowly to handle the fast current transients of the
processor. For this reason, 0805 mid-frequency decoupling capacitors are added on the primary and
secondary side. Some are placed under the package outline of the processor while the rest are
placed in the periphery of the processor along the AF signal row of the pin-map where a majority
of the V
CC-CORE
side power plane flood and Layer 7 ground while using the 0805 capacitors significantly reduces
the inductance of these capacitors. Results from a 3D field solver simulation suggest that an ESL of
600 pH per capacitor may be used to help achieve the specific layout style described in previous
sections. The ESL of the 0805 capacitors is a very critical parameter; the layout style shown in the
recommendation in a latter section shall be closely followed. To stress the importance of 0805
capacitors that result in an ESL of 600 pH, it may be compared to ~1.2 nH ESL for 1206 form
factor capacitors.
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6300ESB ICH Embedded Platform Design Guide
power delivery scheme is shown in
CC-CORE
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M/Celeron M Processor Core Power Delivery
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Intel Pentium
VSS
VSS
9
9
power delivery corridor. Notice the VRM feed point (sense resistor
power pins are found. Four-mil power plane separation between the secondary
January 2007
M Processor Silicon Die
North Side
VCC - CORE
VCC - CORE
9 9
35x10uF
35x10uF
0805 0805
Figure 43.
VR
VR
FEED
FEED
Rsense Rsens e
3 3
+ + + +
- -
8
8
6 6
4x220uF
4x22 0uF
SP Cap
SP Cap
decoupling
CC-CORE
and
CC-CORE
Figure 43.
and GND stitching
CC-CORE
current
CC-CORE
Table 21
93