Power Supply Decoupling Requirements; Thermal Considerations; Package To Board Assembly Process; Silicon Daisy Chain (Sdc) Evaluation Units - Intel PXA27 Series Design Manual

PCB Design Guidelines
2.3

Power Supply Decoupling Requirements

Each major power plane section or feeder trace requires a 4.7 µF or larger bulk decoupling
capacitor near the processor. The processor also requires a 0.1 µF high-frequency decoupling
capacitor on the bottom PCB layer under the package for each group of three to four power supply
pins.
2.4

Thermal Considerations

This subsection describes requirements to ensure the PCB provides adequate thermal dissipation to
ensure compliance with the device operating temperature limitations and long-term reliability.
In battery-powered handset and PDA applications, large heat sinks and forced air cooling are
obviously not practical. For the PXA270 processor, the package heat dissipation is accomplished
primarily using conduction from the 36 center ground balls to the PCB ground plane. For this
reason, the 36 center balls of the VF-BGA package are connected to a solid ground plane under the
package using at least one for every four balls to ensure adequate thermal dissipation.
When the PXA27x processor IC package has a mechanical connection to the product case, this path
also helps dissipate package thermal energy. Refer to Chapter 4 in the Intel
at http://www.intel.com/design/PACKTECH/packbook.htm
thermal requirements.
2.5

Package to Board Assembly Process

Refer to Chapter 14 in the Intel
PACKTECH/packbook.htm
2.6

Silicon Daisy Chain (SDC) Evaluation Units

Intel also offers evaluation units that have been internally shorted together (to the silicon) in a daisy
chain pattern. This ensures that the I/O path of the package is complete through the ball, substrate,
lead beam or bond wire, silicon, and back down through a separate I/O path. These units are useful
for set-up/evaluation of manufacturing equipment.
2.7

Handling: Shipping Media

®
Intel VF-BGA and FS-CSPs are shipped in either tape and reel or in mid-temperature thin matrix
trays that comply with JEDEC standards. All JEDEC standard trays have the same 'x' and 'y'
dimensions and are easily stacked for storage and manufacturing.
I:2-12
®
Packaging Data Book at
for more information on package to board assembly considerations.
®
Intel PXA27x Processor Family Design Guide
®
Packaging Data Book
for more information on package
http://www.intel.com/design/