Reducing Circuit Inductance; Signal Isolation; Power And Ground Planes - Intel Quark SoC X1000 Design Manual

21.11

Reducing Circuit Inductance

Traces should be routed over a continuous reference plane with no interruptions. If
there are vacant areas on a reference or power plane, the signal conductors should not
cross the vacant area. This causes impedance mismatches and associated radiated
noise levels.
21.12

Signal Isolation

To maintain best signal integrity, keep digital signals far away from the analog traces. If
digital signals on other board layers cannot be separated by a ground plane, they
should be routed perpendicular to the differential pairs. If there is another PHY on the
board, the differential pairs from that circuit must be kept away.
Other rules to follow for signal isolation include:
• Separate and group signals by function on separate layers if possible. If possible,
maintain at least a gap of 30 mils between all differential pairs (Ethernet) and other
nets, but group associated differential pairs together.
• Physically group together all components associated with one clock trace to reduce
trace length and radiation.
• Isolate I/O signals from high-speed signals to minimize crosstalk, which can
increase EMI emission and susceptibility to EMI from other signals.
• Avoid routing high-speed LAN traces near other high-frequency signals associated
with a video controller, cache controller, processor, switching power supplies, or
other similar devices.
21.13

Power and Ground Planes

Good grounding requires minimizing inductance levels in the interconnections and
keeping ground returns short, signal loop areas small, and power inputs bypassed to
signal return. This will significantly reduce EMI radiation.
The following guidelines help reduce circuit inductance in both backplanes and
motherboards:
• Route traces over a continuous plane with no interruptions. Do not route over a
split power or ground plane. If there are vacant areas on a ground or power plane,
avoid routing signals over the vacant area. This will increase inductance and EMI
radiation levels.
• All ground vias should be connected to every ground plane; and every power via, to
all power planes at equal potential. This helps reduce circuit inductance.
• Physically locate grounds between a signal path and its return. This will minimize
the loop area.
• Split the ground plane beneath a magnetics module. The RJ-45 connector side of
the transformer module should have chassis ground beneath it.
Caution: DO NOT do this, if the RJ-45 connector has integrated USB.
Note: All impedance-controlled signals should be routed in reference to a solid plane. If there
are plane splits on a reference layer and the signal traces cross those splits then
stitching capacitors should be used within 40 mils of where the crossing occurs. See
Figure 97.
If signals transition from one reference layer to another reference layer then stitching
capacitors or connecting vias should be used based on the following:
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Intel Quark™ SoC X1000
PDG
158
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Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines
June 2014
Order Number: 330258-002US