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2. This evaluation board/kit or development tool is intended for use by an electronic engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind of damage and/or fire caused by its use.
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PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C17W15. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions and operations of the debugging tools, refer to the respective tool manuals.
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3.2 CPU Core ........................3-2 3.2.1 CPU Registers ....................3-2 3.2.2 Instruction Set ....................3-2 3.2.3 Reading PSR ....................3-2 3.2.4 I/O Area Reserved for the S1C17 Core ............3-2 3.3 Debugger ........................3-2 Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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6.2.4 CMOS Output and High Impedance State ............6-3 6.3 Clock Settings ......................... 6-3 6.3.1 PPORT Operating Clock ................... 6-3 6.3.2 Clock Supply in SLEEP Mode ................6-3 6.3.3 Clock Supply in DEBUG Mode ................. 6-3 Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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T16 Ch.n Mode Register ......................11-5 T16 Ch.n Control Register ......................11-5 T16 Ch.n Reload Data Register ....................11-6 T16 Ch.n Counter Data Register ....................11-6 T16 Ch.n Interrupt Flag Register ....................11-6 Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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13.5.3 Data Reception in Master Mode ..............13-7 13.5.4 Terminating Data Transfer in Master Mode ............ 13-8 13.5.5 Data Transfer in Slave Mode ................13-8 13.5.6 Terminating Data Transfer in Slave Mode ............. 13-10 Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Appendix E Initialization Routine ................AP-E-1 Revision History Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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1 OVERVIEW 1 Overview The S1C17W15 is a 16-bit MCU that features low-voltage operation from 1.2 V even though Flash memory is in- cluded. The embedded high-efficiency DC-DC converter generates the constant-voltage to drive the IC with lower power consumption than 4-bit MCUs. This IC includes a real-time clock, a stopwatch, an LCD driver, and a PWM timer capable of being used to generate drive waveforms for a motor driver as well as a high-performance 16-bit CPU.
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OSC1 = 32 kHz, RTC = ON, super economy mode 1.2 µA (100-pin/80-pin package or chip) OSC1 = 32 kHz, RTC = ON, CPU = OSC1, LCD = ON (no panel load, V reference, 1/3 bias, all on), super economy mode Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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(SNDA) #BZOUT CAP10–11 2 Ch. EXCL00–01 EXCL10–11 *1 These pins do not exist in the 64-pin package. *2 These pins do not exist in the 80-pin package. Figure 1.2.1 S1C17W15 Block Diagram Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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O (L) – On-chip debugger status output ✓ ✓ ✓ I/O port ✓ ✓ ✓ DSIO I (Pull-up) – On-chip debugger data input/output ✓ ✓ ✓ I/O port ✓ ✓ ✓ Seiko Epson Corporation 1-10 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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TOUTn0/CAPn0 n = 0, 1 T16B Ch.n PWM output/capture input 0 (T16B) TOUTn1/CAPn1 T16B Ch.n PWM output/capture input 1 Note: Do not assign a function to two or more pins simultaneously. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 1-11 (Rev. 1.3)
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Power supply voltage V ” in the “Electrical Characteristics” chapter and the “Basic External Connection Diagram” chapter, respectively. Note: Be sure to avoid using the V and V pin outputs for driving external circuits. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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PWGINTF.MODCMPIF bit to 1. 2. When a clock source other than OSC1 is started in economy mode The hardware switches to normal mode at the same time the clock source is started. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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(or economy mode). Do not perform heavy- load operations, such as starting a high-speed clock source, before the PWGINTF.MODC- MPIF bit is set to 1, as it may cause a malfunction. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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The reset source refers to causes that request system initialization. The following shows the reset sources. #RESET pin Inputting a reset signal with a certain low level period to the #RESET pin issues a reset request. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Watchdog timer reset #RESET pin Peripheral circuit software reset Reset state is canceled immediately (MODEN and SFTRST bits. The after the reset request is canceled. software reset operations de- pend on the peripheral circuit. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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OSC1 oscillator circuit The OSC1 oscillator circuit is a high-precision and low-power oscillator circuit that uses a 32.768 kHz crystal resonator. Figure 2.3.3.2 shows the configuration of the OSC1 oscillator circuit. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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OSC3 and OSC4 pins may affect the oscillation frequency. • When the internal oscillator is selected, be sure to avoid using the pins to which OSC3 and OSC4 are assigned as input pins, as it may affect the oscillation frequency. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Figure 2.3.4.1 shows the relationship be- tween the oscillation start time and the oscillation stabilization waiting time. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1B[1:0] setting gain INV1N[1:0] setting gain Oscillation waveform Startup boosting Normal operation operation Figure 2.3.4.2 Operation Example when the Oscillation Startup Control Circuit is Used Seiko Epson Corporation 2-10 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Note: Make sure the CLGOSC.OSC3EN bit is set to 0 (while the OSC3 oscillation is halted) when switching the oscillator within three types. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 2-11 (Rev. 1.3)
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CLGSCLK.CLKSRC[1:0] = 0x0 (IOSC) CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC) CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC) ∗ Switching to IOSC that features fast initiation allows high-speed processing. Figure 2.3.4.4 Clock Control Example at SLEEP Cancelation Seiko Epson Corporation 2-12 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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7. The OSC1 oscillation stops if the CLGINTF.OSC1STPIF bit = 1 after an interrupt occurs. If the CLGOSC1.OSDRB bit = 1, the hardware restarts the OSC1 oscillator circuit. Note: Enabling the oscillation stop detection function increase the oscillation stop detector current OSD1 Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 2-13 (Rev. 1.3)
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When a debug interrupt occurs, the CPU enters DEBUG mode. DEBUG mode is canceled when the retd in- struction is executed. For more information on DEBUG mode, refer to “Debugger” in the “CPU and Debugger” chapter. Seiko Epson Corporation 2-14 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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CPU into RUN mode. This transition is executed even if the CPU does not accept the interrupt request. • Interrupt request from a peripheral circuit • NMI • Debug interrupt • Reset request Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 2-15 (Rev. 1.3)
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Operating mode 0x7–0x6 Reserved Super economy mode Reserved Economy mode Normal mode Reserved Automatic mode Note: The PWGCTL.PWGMOD[2:0] bits are set to 0x0 when 0x7, 0x6, 0x4, or 0x1 is written. Seiko Epson Corporation 2-16 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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This bit enables the oscillation startup control circuit in the OSC1 oscillator circuit. 1 (R/WP): Enable (Activate booster operation at startup.) 0 (R/WP): Disable Bit 11 Reserved Bits 10–8 CGI1[2:0] These bits set the internal gate capacitance in the OSC1 oscillator circuit. Seiko Epson Corporation 2-20 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Each bit corresponds to the interrupt as follows: CLGINTE.OSC1STPIE bit: OSC1 oscillation stop interrupt CLGINTE.IOSCTEDIE bit: IOSC oscillation auto-trimming completion interrupt Bit 3 Reserved Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 2-23 (Rev. 1.3)
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0 (R/W): Disable external output Note: Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a glitch may occur when the FOUT output is enabled or disabled. Seiko Epson Corporation 2-24 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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3 CPU AND DEBUGGER 3 CPU and Debugger 3.1 Overview This IC incorporates the Seiko Epson original 16-bit CPU core (S1C17) with a debugger. The main features of the CPU core are listed below. • Seiko Epson original 16-bit RISC processor...
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DBRUN bit, refer to “Clock Supply in DEBUG Mode” in each peripheral circuit chapter. DE- BUG mode continues until a cancel command is sent from the personal computer or the CPU executes the retd in- struction. Neither hardware interrupts nor NMI are accepted during DEBUG mode. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, DSIO pull-up resis- tor R ” in the “Electrical Characteristics” chapter. R is not required when using the DSIO pin as a general- purpose I/O port pin. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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The value (0 or 1) of the PSR Z (zero) flag can be read out with this bit. Bit 0 PSRN The value (0 or 1) of the PSR N (negative) flag can be read out with this bit. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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– 23–0 DBRAM[23:0] *1 Debugging work area start address Bits 31–24 Reserved Bits 23–0 DBRAM[23:0] The start address of the debugging work area (64 bytes) can be read out with these bits. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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For the V voltage, refer to “Recommended Operating Conditions, Flash programming voltage V ” in the “Elec- trical Characteristics” chapter. Note: Always leave the V pin open except when programming the Flash memory. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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The control registers for the peripheral circuits are located in the 8K-byte area beginning with address 0x4000. Table 4.6.1 shows the control register map. For details of each control register, refer to “List of Peripheral Circuit Registers” in the appendix or “Control Registers” in each peripheral circuit chapter. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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P0 Port Interrupt Flag Register 0x4208 P0INTCTL P0 Port Interrupt Control Register 0x420a P0CHATEN P0 Port Chattering Filter Enable Register 0x420c P0MODSEL P0 Port Mode Select Register 0x420e P0FNCSEL P0 Port Function Select Register Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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LCD8B Clock Control Register 0x5402 LCD8CTL LCD8B Control Register 0x5404 LCD8TIM1 LCD8B Timing Control Register 1 0x5406 LCD8TIM2 LCD8B Timing Control Register 2 0x5408 LCD8PWR LCD8B Power Control Register 0x540a LCD8DSP LCD8B Display Control Register Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Note: Once write protection is removed using the MSCPROT.PROT[15:0] bits, write enabled status is maintained until write protection is applied again. After the registers/bits required have been al- tered, apply write protection. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Flash access prohibited The Flash memory can always be accessed during normal operation. Bits 6–2 Reserved Bits 1–0 RDWAIT[1:0] These bits set the number of bus access cycles for reading from the Flash memory. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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FLASHCWAIT.RDWAIT[1:0] bits Number of bus Access cycles System clock frequency 4.2 MHz (max.) 4.2 MHz (max.) 4.2 MHz (max.) 2.1 MHz (max.) Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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ITC if the status is changed to interrupt enabled when the interrupt flag is 1. For specific information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respective pe- ripheral circuit descriptions. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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(0–7) to be set to the IL[2:0] bits in the PSR. The software inter- rupt cannot be disabled (non-maskable interrupt). The processor performs the same interrupt processing operation as that of the hardware interrupt. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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– 2–0 ILVy [2:0] Bits 15–11 Reserved Bits 7–3 Reserved = 2x +1) Bits 10–8 ILVy [2:0] = 2x) Bits 2–0 ILVy [2:0] These bits set the interrupt level of each interrupt. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x = 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). Figure 6.1.1 shows the configuration of PPORT. Table 6.1.1 Port Configuration of S1C17W15 S1C17W15 S1C17W15...
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Falling time (port level = high → low) [second] High level Schmitt input threshold voltage [V] Low level Schmitt input threshold voltage [V] : Pull-up/pull-down resistance [W] Pin capacitance [F] Parasitic capacitance on the board [F] BOARD Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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• Port pins: High impedance state • Port function: Configured to GPIO This status continues until the ports are configured via software. The debugging function ports are configured for debug signal input/output. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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* Steps 1 and 5 are required for the ports with an interrupt function. Step 2 is required for the ports with a chat- tering filter function. Table 6.4.1.1 lists the port status according to the combination of data input/output control and pull-up/down control. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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1. Configure the ports to be used for key-entry reset as general-purpose input ports (refer to “Initial settings when using a port as a general-purpose input port (only for the ports with GPIO function)”). 2. Configure the input pin combination for key-entry reset using the PCLK.KRSTCFG[1:0] bits. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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These bits are used to set data to be output from the GPIO port pins. 1 (R/W): Output high level from the port pin 0 (R/W): Output low level from the port pin Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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PxIOEN.PxIENy bit is set and the port is not pulled up/down. These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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PxMODSEL 15–8 – 0x00 – – 7–0 PxSEL[7:0] 0x00 *1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port. Bits 15–8 Reserved Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Table 6.6.2 Key-Entry Reset Function Settings PCLK.KRSTCFG[1:0] bits key-entry reset Reset when P0[3:0] inputs = all low Reset when P0[2:0] inputs = all low Reset when P0[1:0] inputs = all low Disable Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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A port generated an interrupt 0 (R): No port generated an interrupt The PINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation 6-10 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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The P2 port group supports the GPIO and interrupt functions. Table 6.7.3.1 Control Registers for P2 Port Group Register name Bit name Initial Reset Remarks P2DAT 15–8 P2OUT[7:0] 0x00 – (P2 Port Data 7–0 P2IN[7:0] 0x00 Register) Seiko Epson Corporation 6-12 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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7–0 P3REN[7:0] 0x00 Control Register) P3INTF 15–8 – 0x00 – – (P3 Port Interrupt 7–0 P3IF[7:0] 0x00 Cleared by writing 1. Flag Register) P3IF[7:5] are reserved bits in the 80- pin package. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 6-13 (Rev. 1.3)
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3–2 KRSTCFG[1:0] R/WP 1–0 CLKSRC[1:0] R/WP PINTFGRP 15–8 – 0x00 – – (P Port Interrupt Flag 7–4 – – Group Register) P3INT Reserved bit in the 64-pin package P2INT – P1INT P0INT Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 6-15 (Rev. 1.3)
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4. Initialize the peripheral circuit. 5. Set the PxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) 6. Set the PxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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If the clock source stops in SLEEP mode, WDT stops. To prevent generation of an unnecessary reset after clearing SLEEP mode, reset WDT before executing the slp instruction. WDT should also be stopped as required using the WDTCTL.WDTRUN[3:0] bits. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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WDTCNTRST Always read as 0. 3–0 WDTRUN[3:0] R/WP – Bits 15–5 Reserved Bit 4 WDTCNTRST This bit resets WDT. 1 (WP): Reset 0 (WP): Ignored 0 (R): Always 0 when being read Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Always 0x0 is read if a value other than 0xa is written. Since a reset may be generated immediately after running depending on the counter value, WDT should also be reset concurrently when running WDT. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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* Indicates the status when the pin is configured for RTCA. If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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3. Write 1 to the RTCINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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9.4.4 Stopwatch Count-up Pattern The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 9.4.4.1. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Depending on these operation timings, the +1 second correction may be executed after the count-up operation resumes. For more information on the +1 second correction, refer to “Real-Time Clock Counter Operations.” Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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The RTCALM1.RTCSHA[2:0] bits and the RTCALM1.RTCSLA[3:0] bits set the 10-second digit and 1-second digit of the alarm time, respectively. A value within 0 to 59 seconds can be set in BCD code as shown in Table 9.6.1. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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SWRUN Bits 15–12 BCD10[3:0] Bits 11–8 BCD100[3:0] The 1/10-second and 1/100-second digits of the stopwatch counter can be read as a BCD code from the RTCSWCTL.BCD10[3:0] bits and the RTCSWCTL.BCD100[3:0] bits, respectively. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCSEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 9-10 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 9.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 9-11 (Rev. 1.3)
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The following shows the correspondence between the bit and interrupt: RTCINTF.RTCTRMIF bit: Theoretical regulation completion interrupt RTCINTF.SW1IF bit: Stopwatch 1 Hz interrupt RTCINTF.SW10IF bit: Stopwatch 10 Hz interrupt RTCINTF.SW100IF bit: Stopwatch 100 Hz interrupt Bits 11–9 Reserved Seiko Epson Corporation 9-12 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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The following shows the correspondence between the bit and interrupt: RTCINTE.RTCTRMIE bit: Theoretical regulation completion interrupt RTCINTE.SW1IE bit: Stopwatch 1 Hz interrupt RTCINTE.SW10IE bit: Stopwatch 10 Hz interrupt RTCINTE.SW100IE bit: Stopwatch 100 Hz interrupt Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 9-13 (Rev. 1.3)
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Clock generator CLKDIV[2:0] DBRUN SVDC[4:0] Voltage comparator SVDDT EXSVD circuit Detection SVDSC[1:0] SVDIF result counter SVDIE SVDRE[3:0] Interrupt/reset To system reset circuit control circuit To interrupt controller Figure 10.1.1 SVD Configuration Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 10-1 (Rev. 1.3)
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SLEEP mode and SVD stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD is supplied and the SVD operation resumes. Seiko Epson Corporation 10-2 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the SVDINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Char- acteristics” chapter). Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 10-3 (Rev. 1.3)
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SVDIF bit). An interrupt request is sent to the interrupt controller only when the SVDINTF.SVDIF bit is set while the interrupt is enabled by the SVDINTE.SVDIE bit. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 10-4 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 10-5 (Rev. 1.3)
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SVD detection voltage V 0x1e High 0x1d ↑ 0x1c 0x02 ↓ 0x01 0x00, 0x1f Use prohibited For more information, refer to “Supply Voltage Detector Characteristics, SVD detection voltage ” in the “Electrical Characteristics” chapter. Seiko Epson Corporation 10-6 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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This bit indicates the low power supply voltage detection interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 10-7 (Rev. 1.3)
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• To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 10-8 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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• A clock source and clock division ratio for generating the count clock are selectable. • Repeat mode or one-shot mode is selectable. • Can generate counter underflow interrupts. Figure 11.1.1 shows the configuration of a T16 channel. Table 11.1.1 T16 Channel Configuration of S1C17W15 Item S1C17W15 Number of channels 3 channels (Ch.0–Ch.2)
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(Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 11-2 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 11-3 (Rev. 1.3)
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Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16 Ch.n operating clock (counter clock). Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of T16 Ch.n. Seiko Epson Corporation 11-4 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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PRESET MODEN Bits 15–9 Reserved Bit 8 PRUN This bit starts/stops the timer. 1 (W): Start timer 0 (W): Stop timer 1 (R): Timer is running 0 (R): Timer is idle Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 11-5 (Rev. 1.3)
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This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 11-6 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 11-7 (Rev. 1.3)
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• Input pin can be pulled up with an internal resistor. • The output pin is configurable as an open-drain output. Figure 12.1.1 shows the UART configuration. Table 12.1.1 UART Channel Configuration of S1C17W15 Item S1C17W15 Number of channels 2 channels (Ch.0 and Ch.1)
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When using the UART during SLEEP mode, the UART operating clock CLK_UARTn must be configured so that it will keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_UARTn clock source. Seiko Epson Corporation 12-2 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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(UAnMOD.STPB bit = 1). Parity function The parity function is configured using the UAnMOD.PREN and UAnMOD.PRMD bits. Table 12.4.1 Parity Function Setting UAnMOD.PREN bit UAnMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 12-3 (Rev. 1.3)
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2. Write transmit data to the UAnTXD register. 3. Wait for a UART interrupt when using the interrupt. 4. Repeat Steps 1 to 3 (or 1 and 2) until the end of transmit data. Seiko Epson Corporation 12-4 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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2. Check to see if the UAnINTF.RB1FIF bit is set to 1 (receive buffer one byte full). 3. Read the received data from the UAnRXD register. 4. Repeat Steps 1 to 3 (or 2 and 3) until the end of data reception. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 12-5 (Rev. 1.3)
Page 124
Set the UAnMOD.IRMD bit to 1 to use the IrDA interface. Data transfer control is identical to that for normal interface even if the IrDA interface function is enabled. Seiko Epson Corporation 12-6 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
Page 125
Note, however, that the set timing depends on the buffer status at that point. • When the receive data buffer is empty The interrupt flag will be set when the data that encountered an error is transferred to the re- ceive data buffer. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 12-7 (Rev. 1.3)
Page 126
12.8 Control Registers UART Ch.n Clock Control Register Register name Bit name Initial Reset Remarks UAnCLK 15–9 – 0x00 – – DBRUN 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation 12-8 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
Page 127
1 (R/W): Enable output inverting function 0 (R/W): Disable output inverting function Bit 7 Reserved Bit 6 PUEN This bit enables pull-up of the USINn pin. 1 (R/W): Enable pull-up 0 (R/W): Disable pull-up Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 12-9 (Rev. 1.3)
Page 128
Note: The UAnBR register settings can be altered only when the UAnCTL.MODEN bit = 0. UART Ch.n Control Register Register name Bit name Initial Reset Remarks UAnCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko Epson Corporation 12-10 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
Page 129
PEIF H0/S0 OEIF H0/S0 Cleared by writing 1. RB2FIF H0/S0 Cleared by reading the UAnRXD reg- ister. RB1FIF H0/S0 TBEIF H0/S0 Cleared by writing to the UAnTXD register. Bits 15–10 Reserved Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 12-11 (Rev. 1.3)
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Bit 5 FEIE Bit 4 PEIE Bit 3 OEIE Bit 2 RB2FIE Bit 1 RB1FIE Bit 0 TBEIE These bits enable UART interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Seiko Epson Corporation 12-12 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
Page 132
• Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt. • Input pins can be pulled up/down with an internal resistor. Figure 13.1.1 shows the SPIA configuration. Table 13.1.1 SPIA Channel Configuration of S1C17W15 Item S1C17W15 Number of channels 1 channel (Ch.0)
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16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 13-3 (Rev. 1.3)
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SDIn SDOn (Master mode) SDOn (Slave mode) SDOn (Slave mode) Writing data to the SPInTXD register Figure 13.3.3.1 SPI Clock Phase and Polarity (SPInMOD.LSBFST bit = 0, SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 13-4 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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1. Assert the slave select signal by controlling the general-purpose output port (if necessary). 2. Check to see if the SPInINTF.TBEIF bit is set to 1 (transmit buffer empty). 3. Write transmit data to the SPInTXD register. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 13-5 (Rev. 1.3)
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SPInTXD register Transmit data remained? Wait for an interrupt request (SPInINTF.TBEIF = 1) Negate the slave select signal output from a general-purpose port Figure 13.5.2.2 Data Transmission Flowchart in Master Mode Seiko Epson Corporation 13-6 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Software operations SPInRXD → Data (R) Data (W) → SPInTXD SPInRXD → Data (R) 1 (W) → SPInINTF.TENDIF Figure 13.5.3.1 Example of Data Receiving Operations in Master Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 13-7 (Rev. 1.3)
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SPInTXD register data written is completed. If no transmit data is written during this period, the data bits input from the SDIn pin are shifted and output from the SDOn pin without being modified. Seiko Epson Corporation 13-8 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Data (W) → SPInTXD Data (W) → SPInTXD Software operations SPInRXD → Data (R) SPInRXD → Data (R) Figure 13.5.5.1 Example of Data Transfer Operations in Slave Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 13-9 (Rev. 1.3)
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“Interrupt Controller” chapter. The SPInINTF register also contains the BSY bit that indicates the SPIA operating status. Figure 13.6.1 shows the SPInINTF.BSY and SPInINTF.TENDIF bit set timings. Seiko Epson Corporation 13-10 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Remarks SPInMOD 15–12 – – – 11–8 CHLN[3:0] 7–6 – – PUEN NOCLKDIV LSBFST CPHA CPOL Bits 15–12 Reserved Bits 11–8 CHLN[3:0] These bits set the bit length of transfer data. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 13-11 (Rev. 1.3)
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Note: The SPInMOD register settings can be altered only when the SPInCTL.MODEN bit = 0. SPIA Ch.n Control Register Register name Bit name Initial Reset Remarks SPInCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko Epson Corporation 13-12 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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0x00 – – 6–4 – – OEIF H0/S0 Cleared by writing 1. TENDIF H0/S0 RBFIF H0/S0 Cleared by reading the SPInRXD register. TBEIF H0/S0 Cleared by writing to the SPInTXD register. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 13-13 (Rev. 1.3)
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The following shows the correspondence between the bit and interrupt: SPInINTE.OEIE bit: Overrun error interrupt SPInINTE.TENDIE bit: End-of-transmission interrupt SPInINTE.RBFIE bit: Receive buffer full interrupt SPInINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 13-14 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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• The input filter for the SDA and SCL inputs does not comply with the standard for removing noise spikes less than 50 ns. Figure 14.1.1 shows the I2C configuration. Table 14.1.1 I2C Channel Configuration of S1C17W15 Item S1C17W15 Number of channels 1 channel (Ch.0)
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• The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 14-2 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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14.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 14-3 (Rev. 1.3)
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- Set the I2CnCTL.MST bit to 0. (Set slave mode) - Set the I2CnCTL.SFTRST bit to 1. (Execute software reset) - Set the I2CnCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 14-4 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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I2CnINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condition. When the repeated START condition has been generated, the I2CnINTF.STARTIF and I2CnINTF.TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 14-5 (Rev. 1.3)
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Last data sent? Retry? Write 1 to the I2CnCTL.TXSTOP bit Write data to the I2CnTXD register Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 14-6 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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This reading triggers the I2C Ch.n to start subsequent data reception. Generating a STOP or repeated START condition It is the same as the data transmission in master mode. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 14-7 (Rev. 1.3)
Page 153
Read receive data from the I2CnRXD register Write 1 to the I2CnCTL.TXSTOP bit Write 1 to the I2CnCTL.TXSTOP bit Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.3.2 Master Mode Data Reception Flowchart Seiko Epson Corporation 14-8 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Clear the I2CnINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2CnTXD.TXD[7:1] bits and 1 that represents READ as the data transfer direc- tion to the I2CnTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 14-9 (Rev. 1.3)
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Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2CnINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation 14-10 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 14.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 14-11 (Rev. 1.3)
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I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2CnINTF.RBFIF and I2CnINTF.BYTEENDIF bits are both set to 1. Af- ter that, the received data can be read out from the I2CnRXD register. Seiko Epson Corporation 14-12 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Wait for an interrupt request (I2CnINTF.RBFIF = 1) Last data received next? Write 1 to the I2CnCTL.TXNACK bit Read receive data from the I2CnRXD register Last data received? Figure 14.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 14-13 (Rev. 1.3)
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If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2CnCTL.TXSTART bit to 0 and sets both the I2CnINTF.ERRIF and I2CnINTF.STARTIF bits to 1. Seiko Epson Corporation 14-14 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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4 <Master mode only> When 1 is written to the I2CnCTL.TX- I2CnINTF.ERRIF = 1 START bit while the I2CnINTF.BSY bit = 0 (Refer to “Automatic Automatic bus clearing I2CnCTL.TXSTART = 0 Bus Clearing Operation.”) failure I2CnINTF.STARTIF = 1 Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 14-15 (Rev. 1.3)
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(Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The I2CnCLK register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 14-17 (Rev. 1.3)
Page 163
The I2CnOADR.OADR[9:0] bits are effective in 10-bit address mode (I2CnMOD.OADR10 bit = 1), or the I2CnOADR.OADR[6:0] bits are effective in 7-bit address mode (I2CnMOD.OADR10 bit = 0). Note: The I2CnOADR register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation 14-18 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
Page 164
Bit 0 MODEN This bit enables the I2C operations. 1 (R/W): Enable I2C operations (The operating clock is supplied.) 0 (R/W): Disable I2C operations (The operating clock is stopped.) Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 14-19 (Rev. 1.3)
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0 (R): SDA = High level Bit 11 SCLLOW This bit indicates that SCL is set to low level. 1 (R): SCL = Low level 0 (R): SCL = High level Seiko Epson Corporation 14-20 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
Page 168
- The capture circuit captures counter values using external/software trigger signals and generates interrupts. (Can be used to measure external event periods/cycles.) Figure 15.1.1 shows the T16B configuration. Table 15.1.1 T16B Channel Configuration of S1C17W15 Item S1C17W15 Number of channels 2 channels (Ch.0 and Ch.1)
Page 169
If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 15-2 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Figure 15.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 15-3 (Rev. 1.3)
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- T16BnCTL.CNTMD[1:0] bits (Select count up/down operation) - T16BnCTL.ONEST bit (Select one-shot/repeat operation) - Set the T16BnCTL.PRESET bit to 1. (Reset counter) - Set the T16BnCTL.RUN bit to 1. (Start counting) Seiko Epson Corporation 15-4 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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MAX value. If the MAX value is altered to a value smaller than the current counter value, the counter is cleared to 0x0000 and continues counting up to the new MAX value. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 15-5 (Rev. 1.3)
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MODEN = 1 PRESET = 1 RUN = 1 Software operation Data (W) → MC[15:0] RUN = 1 RUN = 0 Hardware operation 0xffff Count cycle MAX value Counter Time 0x0000 Seiko Epson Corporation 15-6 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
Page 174
Data (W) → MC[15:0] RUN = 1 RUN = 1 0xffff MAX value Counter Time 0x0000 RUN = 0 Figure 15.4.2.3 Operations in Repeat Up/Down Count and One-shot Up/Down Count Modes Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 15-7 (Rev. 1.3)
Page 175
MAX value (T16BnMC register) Counter Comparison value (T16BnCCRm register) Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-8 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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If the captured data stored in the T16BnCCRm register is overwritten by the next trigger when the T16BnINTF. CMPCAPmIF bit is still set, an overwrite error occurs (the T16BnINTF.CAPOWmIF bit is set). Seiko Epson Corporation 15-14 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
Page 183
The TOUT signal polarity (active level) can be set using the T16BnCCCTLm.TOUTINV bit. It is set to active high by setting the T16BnCCCTLm.TOUTINV bit to 0 and active low by setting to 1. Figures 15.4.4.2 and 15.4.4.3 show the TOUT output waveforms. Seiko Epson Corporation 15-16 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16B Ch.n operating clock (counter clock). Bit 3 Reserved Bits 2–0 CLKSRC[2:0] These bits select the clock source of T16B Ch.n. Seiko Epson Corporation 15-22 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
Page 190
T16BnCTL.ONEST bit setting (see Table 15.6.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16BnCTL.CNTMD[1:0] bit settings (see Table 15.6.2). Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 15-23 (Rev. 1.3)
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T16BnCTL.MODEN bit to 1 until the T16BnCS.BSY bit is set to 0 from 1. • Do not set the T16BnMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16BnTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation 15-24 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 15-25 (Rev. 1.3)
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Note: The configuration of the T16BnINTF.CAPOWmIF and T16BnINTF.CMPCAPmIF bits depends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation 15-26 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
Page 194
The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 15-27 (Rev. 1.3)
Page 195
These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16BnCCRm register in capture mode (see Table 15.6.4). The T16BnCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation 15-28 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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The signal becomes inactive by the MATCH signal. All count modes TOUTnm The signal becomes inactive by the MATCHm or MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 15-29 (Rev. 1.3)
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In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation 15-30 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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IC. The buzzer output duration can also be controlled via software. An output start/stop procedure and the SNDA operations are shown below. Normal buzzer output start/stop procedure 1. Set the SNDSEL.MOSEL[1:0] bits to 0x0. (Set normal buzzer mode) Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 16-3 (Rev. 1.3)
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Buzzer signal frequency [Hz] BZOUT DUTY: Buzzer signal duty ratio [%] However, the following settings are prohibited: • Settings as SNDDAT.SFRQ[7:0] bits ≤ SNDDAT.SLEN[5:0] bits • Settings as SNDDAT.SFRQ[7:0] bits = 0x00 Seiko Epson Corporation 16-4 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SND- INTF.SBSY bit is cleared to 0. Figure 16.4.3.1 shows a buzzer output timing chart in one-shot buzzer mode. Seiko Epson Corporation 16-6 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDINTF.SBSY bit is cleared to 0. Figure 16.4.4.1 shows a melody mode operation timing chart. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 16-7 (Rev. 1.3)
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This bit sets whether the SNDA operating clock is supplied in DEBUG mode or not. 1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bit 7 Reserved Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 16-9 (Rev. 1.3)
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193.4 177.7 43.6 162.1 146.5 53.3 129.0 115.2 68.6 99.6 84.0 68.4 52.7 37.1 21.5 Note: Be sure to avoid altering these bits when SNDINTF.SBSY bit = 1. Bits 7–3 Reserved Seiko Epson Corporation 16-10 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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This register functions as a sound buffer. Writing data to this register starts sound output. For detailed information on the setting data, refer to “Buzzer output waveform configuration (normal buzzer mode/one-shot buzzer mode)” and “Melody output waveform configuration.” Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 16-11 (Rev. 1.3)
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No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective The following shows the correspondence between the bit and interrupt: SNDINTF.EMIF bit: Sound buffer empty interrupt SNDINTF.EDIF bit: Sound output completion interrupt Seiko Epson Corporation 16-12 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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These bits enable SNDA interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts The following shows the correspondence between the bit and interrupt: SNDINTE.EMIE bit: Sound buffer empty interrupt SNDINTE.EDIE bit: Sound output completion interrupt Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 16-13 (Rev. 1.3)
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• The LCD contrast is adjustable into 32 steps. • Includes a power supply for 1/3 bias and 1/4 bias driving (allows external voltages to be applied). • Can generate interrupts every frame. Figure 17.1.1 shows the LCD8B configuration. Table 17.1.1 LCD8B Configuration of S1C17W15 S1C17W15 S1C17W15 S1C17W15...
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17.3.1 LCD8B Operating Clock When using LCD8B, the LCD8B operating clock CLK_LCD8B must be supplied to LCD8B from the clock gen- erator. The CLK_LCD8B supply should be controlled as in the procedure shown below. Seiko Epson Corporation 17-2 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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To put LCD8B into external voltage application mode 2, set the LCD8PWR.VCEN bit to 0 to turn the LCD voltage regulator off and the LCD8PWR.BSTEN bit to 1 to turn the LCD voltage booster on. Figure 17.4.3.1 shows an external connection example for external voltage application mode 2. Seiko Epson Corporation 17-4 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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(Enable LCD voltage regulator) - LCD8PWR.VCSEL bit (Set reference voltage for boosting) - LCD8PWR.BISEL bit (Set bias) - LCD8PWR.BSTEN bit (Enable LCD voltage booster) - LCD8PWR.LC[4:0] bits (Set LCD contrast initial value) Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 17-5 (Rev. 1.3)
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RAM. Setting the LCD8DSP.DSPREV bit to 0 inverts the display; setting it to 1 returns the display to normal status. Note that the display will not be inverted when the LCD8DSP.DSPC[1:0] bits = 0x3 (All off). Seiko Epson Corporation 17-6 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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COM4 (= V COM5 (= V COM6 (= V COM7 (= V (= V (= V SEGx (= V (= V (= V Figure 17.5.5.2 1/8 Duty Drive Waveform (1/3 bias) Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 17-9 (Rev. 1.3)
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Figure 17.5.5.3 1/4 Duty Drive Waveform (1/3 bias) 1 frame Frame signal display status (= V COM0 COM0 SEGx (= V SEGx (= V Figure 17.5.5.4 Static Drive Waveform (1/3 bias) Seiko Epson Corporation 17-10 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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In the display data RAM, two screen areas can be allocated and the LCD8DSP.DSPAR bit can be used to switch between the screens. Setting the LCD8DSP.DSPAR bit to 0 selects display area 0; setting to 1 selects display area 1. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 17-11 (Rev. 1.3)
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* In the 80-pin package, addresses 0x701c to 0x701d and 0x705c to 0x705d (when the LCD8DSP.SEGREV bit = 1) or addresses 0x7008 to 0x7009 and 0x7048 to 0x7049 (when the LCD8DSP.SEGREV bit = 0) that are allocated to SEG28 to SEG29 are unused areas (general-purpose RAM). (1) 100-pin package/80-pin package/chip Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 17-13 (Rev. 1.3)
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* In the 80-pin package, addresses 0x701c to 0x701d and 0x705c to 0x705d (when the LCD8DSP.SEGREV bit = 1) or addresses 0x7004 to 0x7005 and 0x7044 to 0x7045 (when the LCD8DSP.SEGREV bit = 0) that are allocated to SEG28 to SEG29 are unused areas (general-purpose RAM). (1) 100-pin package/80-pin package/chip Seiko Epson Corporation 17-16 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the LCD8B operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of the LCD8B. Seiko Epson Corporation 17-18 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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These bits set the frame frequency. For more information, refer to “Frame Frequency.” Bits 7–3 Reserved Bits 2–0 LDUTY[2:0] These bits set the drive duty. For more information, refer to “Drive Duty Switching.” Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 17-19 (Rev. 1.3)
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BSTEN This bit turns the LCD voltage booster on and off. 1 (R/W): LCD voltage booster on 0 (R/W): LCD voltage booster off For more information, refer to “LCD Power Supply.” Seiko Epson Corporation 17-20 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Note: Do not set the LCD8DSP.COMREV bit to 0 when the LCD8TIM1.LDUTY[2:0] bits = 0x4–0x6. Bit 4 DSPREV This bit controls black/white inversion on the LCD display. 1 (R/W): Normal display 0 (R/W): Inverted display Bit 3 Reserved Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 17-21 (Rev. 1.3)
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• Can generate reference oscillation completion, sensor (A and B) oscillation completion, measurement counter overflow error, and time base counter overflow error interrupts. Figure 18.1.1 shows the RFC configuration. Table 18.1.1 RFC Channel Configuration of S1C17W15 Item S1C17W15 Number of channels 4 channels (Ch.0–Ch.3)
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Figure 18.2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 S1C17 RFC : Reference capacitor Figure 18.2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko Epson Corporation 18-2 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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(Clear interrupt flags) - Set the interrupt enable bits in the RFCnINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 18-3 (Rev. 1.3)
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To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 18-4 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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The measurement counter overflow sets the RFCnINTF.EREFIF bit to 1 indicating that the reference oscil- lation has been terminated normally. If the RFCnINTE.EREFIE bit = 1, a reference oscillation completion interrupt request occurs at this point. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 18-5 (Rev. 1.3)
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Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 18.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 18-6 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Bits 7–6 Reserved Bits 5–4 CLKDIV[1:0] These bits select the division ratio of the RFC operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of the RFC. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 18-7 (Rev. 1.3)
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Note: The measurement counter must be set from the low-order value (RFCnMCL.MC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFCnMCH.MC[23:16] bits) is written first. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 18-9 (Rev. 1.3)
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%rs[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,%rs imm7[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,imm7 Output mode setting value Operation mode setting value Figure 19.2.1 Mode Setting Register Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 19-1 (Rev. 1.3)
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16 bits Argument 1 32 bits Operation result S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output (16 bits) Flag output Figure 19.3.1 Data Path in Multiplication Mode Seiko Epson Corporation 19-2 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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16 bits Argument 1 32 bits Operation result S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output Flag output Figure 19.4.1 Data Path in Initialize Mode 2 Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 19-3 (Rev. 1.3)
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*6 R is not required when using the DSIO pin as a general-purpose I/O port. *7 The component values should be determined after evaluating operations using an actual mounting board. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 20-1 (Rev. 1.3)
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, SYSCLK = OSC3, running in the RAM *1 OSC1 oscillator: CLGOSC1.INV1N[1:0] bits = 0x0, CLGOSC1.CGI1[2:0] bits = 0x0, CLGOSC1.OSDEN bit = 0, = 0 pF, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) *2 OSC3 oscillator: CLGOSC3.OSC3MD[1:0] bits = 0x2, CLGOSC3.OSC3INV[1:0] bits = 0x0, C...
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RUN mode (OSC3 operation) IOSC = OFF, OSC1 = 32 kHz, OSC3 = ON, Ta = 25 °C, Typ. value 1,000 Run in Flash Run in RAM Internal oscillator Ceramic oscillator [MHz] OSC3 Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 20-3 (Rev. 1.3)
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Oscillation start time – – µs Oscillation frequency 25 °C 1.6 to 3.6 V IOSC 1.2 to 1.6 V 1.6 to 3.6 V -40 to 85 °C 1.2 to 1.6 V Seiko Epson Corporation 20-4 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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CLGOSC1.OSDEN bit = 1 – 0.025 µA OSD1 *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), = 7 pF) OSC3 oscillator circuit characteristics Unless otherwise specified: V = 1.2 to 3.6 V, V = 0 V, Ta = 25 °C...
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0.8 × V Low level Schmitt input threshold voltage 0.2 × V – 0.5 × V Schmitt input hysteresis voltage – – = 1/f = 1/f EXOSC EXOSC EXOSC EXOSC EXOSCH EXOSCH EXOSC Seiko Epson Corporation 20-6 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Ta = 85 °C, Min. value –V = 1.2 V = 3.6 V = 1.6 V = 1.6 V = 1.2 V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 = 3.6 V Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 20-7 (Rev. 1.3)
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Transfer baud rate Normal mode 1.6 to 3.6 V – 230,400 BRT1 1.2 to 1.6 V – 57,600 IrDA mode 1.6 to 3.6 V – 115,200 BRT2 1.2 to 1.6 V – 57,600 Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 20-9 (Rev. 1.3)
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– – µA SEGH current - 0.1 V, Ta = -40 to 85 °C SEGH SEGxx, COMy – – µA SEGL + 0.1 V, Ta = -40 to 85 °C SEGL Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 20-13 (Rev. 1.3)
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V and V (no panel load) is connected between V and V (no panel load) LCD8PWR.LC[4:0] bits = 0x1f LCD8PWR.LC[4:0] bits = 0x1f LCD8PWR.LC[4:0] bits = 0x00 LCD8PWR.LC[4:0] bits = 0x00 Seiko Epson Corporation 20-14 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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V pin only when a load is connected to the V pin only LCD8PWR.VCSEL bit =1 LCD8PWR.VCSEL bit =1 LCD8PWR.VCSEL bit = 0 LCD8PWR.VCSEL bit = 0 [µA] [µA] Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 20-15 (Rev. 1.3)
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= 3.6 V *1 In this characteristic, unevenness between production lots, and variations in measurement board, resistances and capacitances are taken into account. Waveforms for external clock input mode RFCLK RFCLK RFINn Seiko Epson Corporation 20-16 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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= 1,000 pF, Ta = 25 °C, Typ. value 1,800 1,600 = 3.6 V 1,400 1.6 V 1,200 1.2 V 1,000 = 3.6 V 1.6 V 1.2 V 1,000 Ta [°C] [kHz] RFCLK Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 20-17 (Rev. 1.3)
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*7: The SEG24–SEG33 pins do not exist in the 64-pin package. (24SEG × 4COM/20SEG × 8COM) The SEG28–SEG29 pins do not exist in the 80-pin package. (32SEG × 4COM/28SEG × 8COM) ( ): Do not mount components if unnecessary. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 21-1 (Rev. 1.3)
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Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...
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/0.45 Figure 22.1 SQFN9-64PIN Package Dimensions * The potential of the EXPOSED DIE PAD is the same as that of the substrate potential (V ) on the back of the IC. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL 22-1 (Rev. 1.3)
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• Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL AP-B-1 (Rev. 1.3)
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• Setting the LCD voltage regulator into heavy load protection mode (LCD8PWR.HVLD bit = 1) increases current consumption. Heavy load protection mode should be set only when the display becomes unstable. Seiko Epson Corporation AP-B-2 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues. (1) Connections from the power supply to the V and V pins should be implemented via the shortest, thick- est patterns possible. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL AP-C-1 (Rev. 1.3)
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In this case, C can be omitted by connecting between the V and V pins directly. When these pins are not short-circuited, is required even if super economy mode is not used. Seiko Epson Corporation AP-C-2 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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(2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL AP-C-3 (Rev. 1.3)
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• Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports” chapter. For the UART con- trol and details of receive errors, see the “UART” chapter. Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL AP-D-1 (Rev. 1.3)
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“intXX_handler” can be used for software interrupts. (3) The program code is written in the “.text” section. (4) Sets the stack pointer. (5) Sets the number of Flash memory read cycles. (See the “Memory and Bus” chapter.) Seiko Epson Corporation AP-E-2 S1C17W15 TECHNICAL MANUAL (Rev. 1.3)
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REVISION HISTORY Revision History Code No. Page Contents 412645700 New establishment 412645701 17-2 LCD8B: External Connections (Old) No description (New) Note: When the panel is connected, the LCD8CTL.MODEN bit must be set to 1 to bias the panel even if display is turned off. 20-6 Electrical characteristics: OSC3 CR oscillation frequency-resistance characteristic (Old) f...
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REVISION HISTORY Code No. Page Contents 412645702 ITC: Peripheral Circuit Interrupt Control (Old) Note: To prevent occurrence of unnecessary interrupts, always clear the corresponding interrupt flag before setting the interrupt enable bit to 1 (interrupt enabled) and before terminating the interrupt handler routine.
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REVISION HISTORY Code No. Page Contents 412645702 WDT: During SLEEP mode (Old) WDT operates in SLEEP mode if the selected clock source is running. In this case SLEEP mode is cleared by an NMI or reset if it continues for more than the NMI/reset generation cycle and the NMI or reset handler is executed.
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Min. value were modified.) 21-2 Basic External Connection Diagram: Sample external components (Old) X’tal3 | Crystal resonator | CA-301 (1 MHz) manufactured by Seiko Epson Corporation (New) X’tal3 | Crystal resonator | CA-301 (4 MHz) manufactured by Seiko Epson Corporation AP-A-2 List of Peripheral Circuit Control Registers: CLG OSC3 Control Register Modified the register table (OSC3WT[2:0]: Initial = 0x6 →...
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REVISION HISTORY Code No. Page Contents 412645702 AP-C-2 Mounting Precautions: Unused pins (Old) (4) CV1–2 pins If super economy mode is not used, these pins should be left open. (New) (4) CV1–2 pins If super economy mode is not used, the C and C pins should be left open.
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REVISION HISTORY Code No. Page Contents 412645703 9-11 9.6 Control Registers RTC Month/Day Register Bit 12 RTCMOH Bits 11–8 RTCMOL[3:0] Added a note. Notes: ... • Be sure to avoid setting the RTCMON.RTCMOH/RTCMOL[3:0] bits to 0x00. 10-3 10.4.1 SVD Control Starting detection Corrected Step 4.
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REVISION HISTORY Code No. Page Contents 412645703 20-4 20.4 System Reset Controller (SRC) Characteristics Reset hold circuit characteristics Modified the characteristics table. : Min. = 0.5 ms, Max. = 0.9 ms RSTR 20-7 20.6 Flash Memory Characteristics Added an annotation. *1 The potential variation of the V voltage should be suppressed to within ±0.3 V on the basis of the ground potential of the MCU mounting board while the Flash is being programmed, as it affects the...