16-Bit Free-Run Timer; Fig. 11.4 Clearing Counter By Overflow; Fig. 11.5 Clearing Counter When Value Of 16-Bit Free-Run Timer Matches Value Of Compare Clear Register - Fujitsu MB90420/5 (A) Series Hardware Manual

11.4.2 16-bit Free-run Timer

After a reset is canceled, the 16-bit free-run timer starts counting at 0000. This counter value works as the
base time of the 16-bit output compare and 16-bit input capture.
n Operation of 16-bit free-run timer
The counter value the is cleared at the following conditions.
• When an overflow occurs
• When a compare clear register value and compare match (mode setting is required)
• When 1 is written to the SCLR bit of the TCCS register during operation
• When 0000
is written to the TCDT register while timer stops
H
An interrupt can be generated when an overflow occurs and the counter is cleared at a compare match with
the value of compare clear register (a compare match interrupt needs mode seting).
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
Interrupt
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
Compare register
Interrupt
Fig. 11.5 Clearing Counter when Value of 16-bit Free-run Timer Matches
INPUT CAPTURE

Fig. 11.4 Clearing Counter by Overflow

BFFF
H
Value of Compare Clear Register
11-15
Time
Time