Interrupt Acceptance, Levels And Modes - Fujitsu F2MC-FR Series Application Note

2.3 Interrupt Acceptance, Levels and Modes

The following table explains various interrupts/exceptions, corresponding levels, acceptance
conditions etc.
Exception/
Interrupt/ Description
Trap
Exception Undefined
Instruction
Trap INTE Instruction
Trap INT Instruction
Interrupt NMI
Trap Step Trace Trap
Trap Coprocessor
Exception
© Fujitsu Microelectronics Europe GmbH
INTERRUPTS
Chapter 2 Interrupt Types
Interrupt/
Interrupt
Vector
Level
Number
14 No Level
9 Always
Fixed, 4
0 to 255, No Level
As
specified
by
operand
15 Always
Fixed, 15
12 Always
Fixed, 4
7 & 8 No Level
- 9 -
Acceptance
Condition
Always Accepted
Always Accepted
Always Accepted
Current instruction
execution is finished
If ILM (Interrupt Level
Mask) of PS
(Processor Status )
register is greater
than 15
Always Accepted
MCU-AN-300055-E-V10
Action after Acceptance
Save CPU status to system
stack
S = 0 (use system stack)
I = 0 i.e. all peripheral
interrupts are suspended until
Undefined Instruction ISR
execution, Undefined
Instruction ISR can not be
interrupted
Branch to interrupt vector
Save CPU status to system
stack
S = 0 (use system stack)
ILM = 4 i.e. all
traps/interrupts/exceptions
suspended until INTE ISR
execution
Branch to interrupt vector
Save CPU status to system
stack
S = 0 (use system stack)
I = 0 i.e. all peripheral
interrupts are suspended until
INT ISR execution, INT ISR
can be interrupted by NMI,
Undefined Instruction, Step
Trace Trap and INTE
Instruction
Branch to interrupt vector
Save CPU status to system
stack
S = 0 (use system stack)
ILM = 15 i.e. all peripheral
interrupts are suspended until
NMI ISR execution, NMI ISR
can be interrupted by
Undefined Instruction, Step
Trace Trap and INTE
Instruction
Branch to interrupt vector
Save CPU status to system
stack
S = 0 (use system stack)
ILM = 4 i.e. all
traps/interrupts/exceptions
suspended until Step Trace
ISR execution
Branch to interrupt vector
Save CPU status to system
stack
S = 0 (use system stack)
I = 0 i.e. all peripheral
interrupts are suspended until
Coprocessor Exception ISR