TDT RZ2 Manual page 58

1-52
time applications or custom applications. This manual includes device specific
information needed during circuit design. For circuit design techniques and a complete
reference of the RPvdsEx circuit components, see "MultiProcessor Circuit Design" and
"Multi-Channel Circuit Design" in the
RZ5 Architecture
The RZ5 processor utilizes a multi-bus architecture and offers three dedicated, data
buses for fast, efficient data handling. While the operation of the system architecture
is largely transparent to the user, a general understanding is important when
developing circuits in RPvdsEx.
As shown in the diagram above, the RZ5 architecture consists of three
functional blocks:
The DSPs
RZ5 BioAmp Processor
RPvdsEx Manual
Each DSP in the DSP Block is connected to 64 MB
SDRAM and a local interface to the three data buses: two
buses that connect each DSP to the other functional blocks
and one that handles data transfer between the DSPs (as
described further in Distributing Data Across DSPs below).
This architecture facilitates fast DSP-to-off-chip data
handling.
Because each DSP has its own associated memory, access
is very fast and efficient. However, large and complex
circuits should be designed to balance memory needs (such
as data buffers and filter coefficients) across processors.
When designing circuits also note that the maximum number
of components for each RZ5 DSP is 768.
System 3
.