Timer Interrupt Enable Register (Tier) - Hitachi H8/3032 Series Hardware Manual

Downloaded from Elcodis.com electronic components distributor

8.2.13 Timer Interrupt Enable Register (TIER)

TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel Abbreviation Function
0 TIER0 Enables or disables interrupt requests.
1 TIER1
2 TIER2
3 TIER3
4 TIER4
Bit 7
—
Initial value 1
Read/Write —
Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt
requests and general register compare match and input capture interrupt requests.
TIER is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
6 5 4 3
— — — —
1 1 1 1
— — — —
Reserved bits
Overflow interrupt enable
Enables or disables OVF
interrupts
Input capture/compare match
interrupt enable B
Enables or disables IMFB interrupts
203
2 1 0
OVIE IMIEB IMIEA
0 0 0
R/W R/W R/W
Input capture/compare match
interrupt enable A
Enables or disables IMFA
interrupts