Controller Overview; Programming Model - Motorola MC68302 User Manual

This function may be implemented in two SCCs. One SCC operates as a
UART; the other SCC operates as a V.110 controller. The M68000 core formats
the data for transmission by the V.110 at the 64 kbps data rate. Thus, the
RA 1 step is hidden in software.
4.5.15.4 V.110 CONTROLLER OVERVIEW. By the appropriate setting of its SCC
mode register, any of the SCC channels may be configured to function as a
V.110 controller. MODE1-MODEO bits the SCC mode register should be pro-
grammed to DDCMP, and the V.110 bit in the DDCMP mode register should
be set. The V.110 controller has the ability to receive and transmit V.110 80-
bit frames. The processing of those frames is handled by the M68000 core
in software.
The V.110 receiver will synchronize on the 17-bit alignment pattern of the
frame:
00000000
1xxxxxxx
1xxxxxxx 1xxxxxxx 1xxxxxxx
1xxxxxxx 1xxxxxxx
1xxxxxxx
1xxxxxxx
1xxxxxxx
After achieving frame synchronization, the receiver will transfer the frame
data to a receive buffer (the leading one will be the MSB). The V.110 controller
will write nine bytes of data to the buffer (discarding the first byte of all zeros).
The M68000 core should unformat the data in memory according to the V.110
protocol to create the data buffer; it may then use another SCC controller to
transmit this data to the R interface.
The V.110 transmitter will transmit a data buffer transparently with a bit swap
(the MSB will be transmitted first) onto a B channel. The data buffer should
contain the 17-bit alignment pattern. Another SCC controller may be used to
receive data from the R interface. The M68000 core should then format the
data according to the V.110 protocol to create the V.110 80-bit frame data
buffer. The V.110 controller will then transmit it onto the B channel.
The V.110 controller operates on the ISDN physical interface using either IDL
or GCI (IOM-2) over one of the B channels. NMSI and PCM physical interfaces
are also possible. The data synchronization register (DSR) should be pro-
grammed to 'xxxxxxx1 OOOOOOOO'b to achieve the proper frame synchroniz-
ation (see 4.5.4 SCC Data Synchronization Register (DSR)).
4.5.15.5 V.110 PROGRAMMING MODEL. The M68000 core configures each
sec
to operate in one of the protocols by the MODE1-MODEO bits in the SCC
4-104 MC68302 USER'S MANUAL
MOTOROLA