Overview - Motorola CPU32 Reference Manual

SECTION 1
OVERVIEW
The CPU32, the first-generation instruction processing module of the M68300
Family, is based on the industry-standard MC68000 processor. It has many
features of the MC68010 and MC68020, as well as unique features suited for
high-performance controller applications. The CPU32is source code and
binary code compatible with the M68000 Family.
CPU32 power consumption during normal operation is low because it is a high-
speed complementary metal-oxide semiconductor (HCMOS) device. Power
consumption can be reduced to a minimum during periods of inactivity by
executing the low-power stop (LPSTOP) instruction, which shuts down the
CPU32 and other intermodule bus (1MB) submodules.
Ease of programming is an important consideration in using a microcontroller.
The CPU32 instruction format reflects a predominately register-memory
interaction philosophy. All data resources are available to all operations
requiring those resources. There are eight multifunction data registers and
seven general-purpose addressing registers. The data registers readily support
8-bit (byte), 16-bit (word), and 32-bit (long word) operand lengths for all
operations. Address manipulation is supported by word and long-word
operations. Although the program counter (PC) and stack pointers (SP) are
special-purpose registers, they are also available for most data addressing
activities. Ease of program checking and diagnosis is enhanced by trace and
trap capabilities at the instruction level.
As controller applications become more complex and control programs become
larger, high-level language (HLL) will become the system designer's choice in
programming languages. HLL aids rapid development of complex algorithms,
with less error, and is readily portable. The CPU32 instruction set will efficiently
support HLL.
CPU32 REFERENCE MANUAL OVERVIEW MOTOROLA
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