Underflow Operation; Figure 15.4.2A Underflow Operation - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

15.4.2 Underflow operation

An underflow is defined for this timer as the time when the counter value changes from 0000
Therefore, an underflow occurs after (reload register setting + 1) counts.
If the RELD bit in the control register is "1" when the underflow occurs, the contents of the reload register is
loaded into the counter and counting continues. When RELD is "0", counting stops with the counter at
FFFF .
H
The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at this time, an
interrupt request is generated.
Figure 15.4.2a shows the operation when an underflow occurs.
Count clock
Counter
Data load
Underflow set
Count clock
Counter
Underflow set
MB90580 Series
Reload data
0000
H
[RELD=1]
0000 FFFF
H
H
[RELD=0]

Figure 15.4.2a Underflow Operation

Chapter 15: 16-Bit Reload Timer (with Event Count Function)
15.4 Operation
-1 -1
to FFFF .
H H
-1
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