Table Of Contents - ST STM32F413 Reference Manual

RM0430 List of figures
Figure 250. Transfer Sequence Flowchart For Fmpi2C Slave Transmitter, Nostretch=1 . . . . . . . . . 770
Figure 251. Transfer Bus Diagrams For Fmpi2C Slave Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
Figure 252. Transfer Sequence Flowchart For Slave Receiver With Nostretch=0 . . . . . . . . . . . . . . . 772
Figure 253. Transfer Sequence Flowchart For Slave Receiver With Nostretch=1 . . . . . . . . . . . . . . . 773
Figure 254. Transfer bus diagrams for FMPI2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Figure 255. Master Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Figure 256. Master Initialization Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Figure 257. 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Figure 258. 10-Bit Address Read Access With Head10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
Figure 259. Transfer sequence flowchart for FMPI2C master transmitter for N≤255 bytes. . . . . . . . . 779
Figure 260. Transfer sequence flowchart for FMPI2C master transmitter for N>255 bytes. . . . . . . . . 780
Figure 261. Transfer Bus Diagrams For Fmpi2C Master Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Figure 262. Transfer sequence flowchart for FMPI2C master receiver for N≤255 bytes . . . . . . . . . . . 783
Figure 263. Transfer sequence flowchart for FMPI2C master receiver for N >255 bytes . . . . . . . . . . 784
Figure 264. Transfer Bus Diagrams For Fmpi2C Master Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
Figure 265. Timeout intervals for t , t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
LOW:SEXT LOW:MEXT
Figure 266. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . 792
Figure 267. Transfer Bus Diagrams For Smbus Slave Transmitter (Sbc=1) . . . . . . . . . . . . . . . . . . . . . 793
Figure 268. Transfer Sequence Flowchart For Smbus Slave Receiver N Bytes + Pec . . . . . . . . . . . . . 794
Figure 269. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1) . . . . . . . . . . . . . . . . . . . . . . . 795
Figure 270. Bus Transfer Diagrams For Smbus Master Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Figure 271. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
Figure 272. FMPI2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Figure 273. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
Figure 274. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Figure 275. Transfer Sequence Diagram For Slave Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
Figure 276. Transfer Sequence Diagram For Slave Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
Figure 277. Transfer Sequence Diagram For Master Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
Figure 278. Transfer Sequence Diagram For Master Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
Figure 279. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Figure 280. Usart Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
Figure 281. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
Figure 282. Configurable Stop Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
Figure 283. Tc/Txe Behavior When Transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
Figure 284. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
Figure 285. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
Figure 286. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
Figure 287. Mute Mode Using Idle Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Figure 288. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
Figure 289. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set) . . . . . . . . . . . . . . . . . 883
Figure 290. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 884
Figure 291. Usart Example Of Synchronous Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
Figure 292. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
Figure 293. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
Figure 294. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
Figure 295. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
Figure 296. Parity Error Detection Using The 1.5 Stop Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
Figure 297. Irda Sir Endec- Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Figure 298. IrDA data modulation (3/16) -Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Figure 299. Transmission Using Dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
Figure 300. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
Figure 301. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
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