Table Of Contents - ST STM32F413 Reference Manual

RM0430
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
6.3.17
6.3.18
6.3.19
6.3.20
6.3.21
6.3.22
6.3.23
6.3.24
6.3.25
6.3.26
6.3.27
6.3.28
6.3.29
6.3.30
7 General-Purpose I/Os (Gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
7.1 GPIO introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr) . . . . . . . . . . 136
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
For Stm32F413Xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
For Stm32F423Xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Rcc Ahb3 Peripheral Reset Register (Rcc_Ahb3Rstr) . . . . . . . . . . 140
RCC APB1 peripheral reset register for (RCC_APB1RSTR) . . . . . . . 140
Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr) . . . . . . . . . . 144
Rcc Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr) . . . . . 146
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
For Stm32F413Xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
For Stm32F423Xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Rcc Ahb3 Peripheral Clock Enable Register (Rcc_Ahb3Enr) . . . . . 150
RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . 150
RCC APB2 peripheral clock enable register
(RCC_APB2ENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) for STM32F413xx . . . . . . . . . . . . . . . . . . . . . . . 159
RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) for STM32F423xx . . . . . . . . . . . . . . . . . . . . . . . 160
RCC AHB3 peripheral clock enable in low power mode register
(RCC_AHB3LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Rcc Backup Domain Control Register (Rcc_Bdcr) . . . . . . . . . . . . . . 168
RCC clock control & status register (RCC_CSR) . . . . . . . . . . . . . . . . 169
Rcc Spread Spectrum Clock Generation Register (Rcc_Sscgr) . . . . 171
Rcc Plli2S Configuration Register (Rcc_Plli2Scfgr) . . . . . . . . . 172
Rcc Dedicated Clocks Configuration Register (Rcc_Dckcfgr) . . 174
Rcc Clocks Gated Enable Register (Ckgatenr) . . . . . . . . . . . . . . . . 176
Rcc Dedicated Clocks Configuration Register (Rcc_Dckcfgr2) . 177
Rcc Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
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